MAX886ECJ Просмотр технического описания (PDF) - Maxim Integrated
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MAX886ECJ Datasheet PDF : 20 Pages
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Wireless and Satellite Handset
Power-Management ICs
Pin Description (continued)
PIN
NAME
FUNCTION
24
OUT1
Linear Regulator 1 Output. Bypass with a 2.2µF, low-ESR capacitor to GND. Up to 100mA is available from
OUT1.
25
OFF
Power-Off Input. Drive OFF high before the startup timer has expired in order to keep the IC powered on.
Drive OFF low to shut down the IC. OFF has an internal 100kΩ pulldown resistor to GND.
26
ON
Power-On Input. Pulse the ON pin low to turn on the IC. ON has an internal 16µA pullup resistor.
27
ONSTAT
ON Status Output. Push-pull logic output indicating the state of the ON input. The logic state of this pin
follows the logic state of the ON pin. The logic high output voltage is the output voltage of OUT2.
28
SDA
Serial Interface Data Input
29
SCL
Serial Interface Clock Input
Sync Input. Drive SYNC with a logic-level square wave to synchronize the internal oscillator. The capture
30
SYNC range for external clock is ±20% of the selected internal oscillator frequency. Drive SYNC low for more
than 10µs to force low-power PFM mode (standby mode). Drive SYNC high to force PWM mode.
31
CVH
High-Side Drive Bypass Input. Bypass CVH with a 0.1µF capacitor connected to IN0.
32
IN0
Regulator 0 Power-Supply Input. Connect to BATT. Source of the internal P-channel MOSFET.
A
B
C
D
EF
G
tLOW tHIGH
SCL
H
IJ
K
LM
SDA
tSU:STA tHD:STA
tSU:DAT
tHD:DAT
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE (OP/SUS BIT)
H = LSB OF DATA CLOCKED INTO SLAVE
I = SLAVE PULLS SMBDATA LINE LOW
Figure 1. I2C-Compatible Serial-Interface Timing Diagram
tSU:STO tBUF
J = ACKNOWLEDGE CLOCKED INTO MASTER
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION, DATA EXECUTED BY SLAVE
M = NEW START CONDITION
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