SPT9691 Просмотр технического описания (PDF) - Signal Processing Technologies

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SPT9691

WIDE INPUT VOLTAGE, JFET COMPARATOR

Signal Processing Technologies 

TIMING INFORMATION

The timing diagram for the comparator is shown in figure 1.

If LE is high and LE low in the SPT9691, the comparator

tracks the input difference voltage. When LE is driven low

and LE high, the comparator outputs are latched into their

existing logic states.

The leading edge of the input signal (which consists of a

150 mV overdrive voltage) changes the comparator output

after a time of tpdL or tpdH (Q or Q ). The input signal must be

maintained for a time ts (set-up time) before the LE falling

edge and LE rising edge and held for time tH after the falling

edge for the comparator to accept data. After tH , the output

ignores the input status until the latch is strobed again. A

minimum latch pulse width of tpL is needed for strobe opera-

tion, and the output transitions occur after a time of tpLOH or

tpLOL.

Figure 1 - Timing Diagram

Latch Enable

Latch Enable

Differential

Input Voltage

Output Q

tH

tS

VOD

tpdL

tpL

t pLOH

50%

VRef ± VOS

50%

Output Q

tpdH

tpLOL

50%

VIN +=300 mV, VOD=150 mV

The set-up and hold times are a measure of the time required for an input signal to propagate through the

first stage of the comparator to reach the latching circuitry. Input signals occurring before ts will be detected

and held; those occurring after tH will not be detected. Changes between tS and tH may not be detected.

SWITCHING TERMS (Refer to figure 1)

tpdH INPUT TO OUTPUT HIGH DELAY - The propagation

delay measured from the time the input signal crosses

the reference voltage (± the input offset voltage) to the

50% point of an output LOW to HIGH transition.

tpdL INPUT TO OUTPUT LOW DELAY - The propagation

delay measured from the time the input signal crosses

the reference voltage (± the input offset voltage) to the

50% point of an output HIGH to LOW transition.

tpLOH LATCH ENABLE TO OUTPUT HIGH DELAY - The

propagation delay measured from the 50% point of the

Latch Enable signal LOW to HIGH transition to 50%

point of an output LOW to HIGH transition.

tpLOL LATCH ENABLE TO OUTPUT LOW DELAY - The

propagation delay measured from the 50% point of the

Latch Enable signal LOW to HIGH transition to the 50%

point of an output HIGH to LOW transition.

tH MINIMUM HOLD TIME - The minimum time after the

negative transition of the Latch Enable signal that the

input signal must remain unchanged in order to be

acquired and held at the outputs.

tpL MINIMUM LATCH ENABLE PULSE WIDTH - The

minimum time that the Latch Enable signal must be

HIGH in order to acquire an input signal change.

tS MINIMUM SET-UP TIME - The minimum time before

the negative transition of the Latch Enable signal that

an input signal change must be present in order to be

acquired and held at the outputs.

VOD VOLTAGE OVERDRIVE - The difference between the

differential input and reference input voltages.

SPT

4

SPT9691

10/6/97

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