X25649 Просмотр технического описания (PDF) - Xicor -> Intersil
Номер в каталоге
Компоненты Описание
производитель
X25649 Datasheet PDF : 16 Pages
| |||
X25648/49, X25328/29, X25168/69
The read only FLAG bit shows the status of a volatile latch
that can be set and reset by the system using the SFLB
and RFLB instructions. The Flag bit is automatically reset
upon power up.
The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with the
WP pin to provide Programmable Hardware Write Protec-
tion (Table 2). When WP is LOW and the WPEN bit is pro-
grammed HIGH, all Status Register Write Operations are
disabled.
In Circuit Programmable ROM Mode
This mechanism protects the Block Lock and Watchdog
bits from inadvertant corruption. It may be used to per-
form an In Circuit Programmable ROM function by hard-
wiring the WP pin to ground, writing and Block Locking
the desired portion of the array to be ROM, and then pro-
gramming the WPEN bit HIGH.
Read Sequence
When reading from the E2PROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the 16-
bit address. After the READ opcode and address are
sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored in
memory at the next address can be read sequentially by
continuing to provide clock pulses. The address is auto-
matically incremented to the next higher address after
each byte of data is shifted out. When the highest address
is reached, the address counter rolls over to address
$0000 allowing the read cycle to be continued indefinitely.
The read operation is terminated by taking CS high. Refer
to the Read E2PROM Array Sequence (Figure 1).
To read the Status Register, the CS line is first pulled low
to select the device followed by the 8-bit RDSR instruc-
tion. After the RDSR opcode is sent, the contents of the
Status Register are shifted out on the SO line. Refer to
the Read Status Register Sequence (Figure 2).
Write Sequence
Prior to any attempt to write data into the device, the
“Write Enable” Latch (WEL) must first be set by issuing
the WREN instruction (Figure 3). CS is first taken LOW,
then the WREN instruction is clocked into the device.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the Write
Operation without taking CS HIGH after issuing the
WREN instruction, the Write Operation will be ignored.
To write data to the E2PROM memory array, the user then
issues the WRITE instruction followed by the 16 bit
address and then the data to be written. Any unused bits
are specified to be “0’s”. The WRITE operation minimally
takes 32 clocks. CS must go low and remain low for the
duration of the operation. If the address counter reaches
the end of a page and the clock continues, the counter will
roll back to the first address of the page and overwrite any
data that may have been previously written.
For the Page Write Operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of the
last data byte to be written is clocked in. If it is brought
HIGH at any other time, the write operation will not be
completed (Figure 4).
To write to the Status Register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits 0
and 1 must be “0”. Data bits 4 and 5 must be “1”.
Table 2.
STATUS
REGISTER
STATUS
REGISTER
WEL
0
1
1
1
WPEN
X
1
0
X
DEVICE
PIN
WP#
X
0
X
1
BLOCK
PROTECTED
BLOCK
Protected
Protected
Protected
Protected
BLOCK
UNPROTECTED
BLOCK
Protected
Writable
Writable
Writable
STATUS
REGISTER
WPEN, BL0,
BL1 BITS
Protected
Protected
Writable
Writable
7036 FRM T06
4
Share Link: 