ML4841CP(V2) Просмотр технического описания (PDF) - Fairchild Semiconductor
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ML4841CP Datasheet PDF : 13 Pages
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ML4841
PRODUCT SPECIFICATION
PWM SECTION
Pulse Width Modulator
The PWM section of the ML4841 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, to which it also provides its basic
timing. The PWM operates in current-mode. In applications
utilizing current mode control, the PWM ramp (RAMP 2) is
usually derived directly from a current sensing resistor or
current transformer in the primary of the output stage, and is
thereby representative of the current flowing in the con-
verter’s output stage. The DC ILIMIT comparator provides
cycle-by-cycle current limiting and is connected to RAMP 2
internally. If the current sense signal exceeds the 1V thresh-
old, the PWM switch is disabled until the protection flip-flop
is rest by the clock pulse at the start of the next PWM power
cycle.
PWM Current Limit
The DC ILIMIT comparator is a cycle-by-cycle current lim-
iter for the PWM section. Should the input voltage at this pin
ever exceed 1V, the output of the PWM will be disabled until
the output flip-flop is reset by the clock pulse at the start of
the next PWM power cycle.
VIN OK Comparator
The VIN OK comparator monitors the DC output of the PFC
and inhibits the PWM if this voltage on VFB is less than its
nominal 2.5V. Once this voltage reaches 2.5V, which
corresponds to the PFC output capacitor being charged to its
rated boost voltage, the soft-start commences.
PWM Control (RAMP 2)
The PWM section utilizes current mode control. RAMP 2
is generally used as the sampling point for a voltage
representing the current in the primary of the PWM’s output
transformer, derived either by a current sensing resistor or a
current transformer.
Soft Start
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 50µA supplies
the charging current for the capacitor, and start-up of the
PWM begins at 1.25V. Start-up delay can be programmed by
the following equation:
CSS = tDELAY × 1-5---.0--2--µ-5---A-V--
(11)
where CSS is the required soft start capacitance, and tDELAY
is the desired start-up delay.
It is important that the time constant of the PWM soft-start
allows the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at least
5ms.
Solving for the minimum value of CSS:
CSS = 5ms × 1-5---.0--2--µ-5---A-V-- = 200nF
VBIAS
VCC
ML4841
GND
10nF
ceramic
1µF
ceramic
Figure 3. External Component Connections to VCC
Generating VCC
The ML4841 is a current-fed part. It has an internal shunt
voltage regulator, which is designed to regulate the voltage
internal to the part at 13.5V. This allows a low power dissi-
pation while at the same time delivering 10V of gate drive at
the PWM OUT and PFC OUT outputs. It is important to
limit the current through the part to avoid overheating or
destroying it. This can be easily done with a single resistor in
series with the Vcc pin, returned to a bias supply of typically
18V to 20V. The resistor’s value must be chosen to meet the
operating current requirement of the ML4841 itself (19mA
max) plus the current required by the two gate driver outputs.
EXAMPLE:
With a VBIAS of 20V, a VCC limit of 14.6V (max) and
driving a total gate charge of 100nC at 100kHz (1 IRF840
MOSFET and 2 IRF830 MOSFETs), the gate driver current
required is:
IGATEDRIVE = (100kHz × 45nC) + (200kHz × 52nC) =15mA (12)
RBIAS = 1----29---0-m---V--A---–--+---1--1-4---5.--6-m---V---A-- = 160Ω
(13)
To check the maximum dissipation in the ML4841, check the
current at the minimum VCC (12.4V):
ICC = 2----0----V--1---6–---0--1--Ω-2---.--4----V-- = 47.5mA
(14)
The maximum allowable ICC is 55mA, so this is an accept-
able design.
10
REV. 1.0.3 6/13/01
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