UTR200 Просмотр технического описания (PDF) - Aeroflex UTMC

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UTR200

UTR 0.8μ Gate Array Family

Aeroflex UTMC 

ASIC DESIGN SOFTWARE

Using a combination of state-of-the-art third-party and propri-

etary design tools, UTMC delivers the CAE support and

capability to handle complex, high-performance ASIC designs

from design concept through design verification and test.

DESIGN CREATION

UTMC’s flexible design creation methodology supports high

level design by providing UTR 0.8µ cell libraries for synthesis.

Using Mentor Graphics and Synopsys synthesis tools, a

structural design can be created for verification in VITAL-

compliant VHDL or the Mentor Graphics environment.

UTMC’s cell libraries also support Automatic Test Program

Generation (ATPG) to improve design testing.

DESIGN ANALYSIS

UTMC’s design analysis tools check the integrity of the design

and ensure that it can be manufactured in UTMC processes.

Design analysis tools include:

DESIGN ANALYSIS

TOOL

Logic Rules Checker

FUNCTION

Makes sure the design meets

connectivity rules

Tester Rules Checker

Makes sure the design can be

tested on UTMC testers

Design Transfer Tool

Allows accurate transfer of

design data to UTMC

TOOLS SUPPORTED BY UTMC

MENTOR

GRAPHICS

AutoLogicII®

QuickSimII®

QuickFault II®

QuickGradeII®

FastScan ®/

FlexTest® /

DFT Advisor®

SYNOPSYS

Design CompilerTM

VHDL CompilerTM

TestSimTM

Verilog HDL

CompilerTM

Test Compiler

PlusTM

VHDL

Synopsys

VSSTM

Mentor

Graphics

Quick-

HDL®

Cadence

Leapfrog®

Viewlogic

VantageTM

Any

VITAL-

compliant

VHDL tool

XDTSM (EXTERNAL DESIGN TRANSLATION)

Through UTMC’s XDT services, customers can convert an

existing non-UTMC design to UTMC’s processes. The XDT

tool is particularly useful for converting an FPGA to a UTMC

radiation-hardened gate array. The XDT translation tools

convert industry standard netlist formats and vendor libraries to

UTMC formats and libraries. Industry standard netlist formats

supported by UTMC include:

• VHDL

• Verilog HDLTM

• FPGA source files (Actel, Altera, Xilinx)

• EDIF

• Third-party netlists supported by Synopsys

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