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UTR200

UTR 0.8μ Gate Array Family

Aeroflex UTMC 

Extensive Cell Library

The UTR 0.8µ family of gate arrays is supported by an extensive

cell library that includes SSI, MSI, and 54XX-equivalent func-

tions, as well as, RAM and other megafunctions. User-

selectable options for cell configurations include scan for all

register elements, as well as output drive strength. UTMC’s

megacell library includes the following functions:

• Intel® 80C31 equivalent

• MIL-STD-1553 functions (BCRTM, RTI, RTMP)

• MIL-STD-1750 microprocessor

• Standard microprocessor peripheral functions

• Configurable RAM

Refer to UTMC’s UTR 0.8µ Design Manual for complete cell

listing and details.

I/O Buffers

The UTR 0.8µ gate array family offers up to 342 device pad

locations (note: device pad availability is affected by package

selection and pinout.) The I/O cells can be configured by the

user to serve as input, output, bidirectional, three-state, or addi-

tional power and ground pads. Output drive options range from

2 to 8mA. To drive larger off-chip loads, output drivers can be

combined in parallel to provide additional drive up to 12mA.

Other I/O buffer features and options include:

• Slew rate control

• Pull-up and pull-down resistors

• TTL, CMOS, and Schmitt levels

• Built-in boundary-scan

JTAG Boundary-Scan

The UTR 0.8µ arrays include a test access port and boundary-

scan architecture that conforms to the IEEE Standard 1149.1

(JTAG). Some of the benefits this capability offers include the

following:

• Allows easy test of complex assembled printed circuit

boards

• Can be used to gain access to and control internal

scan paths

• Can be used to initiate Built-In Self Test

Clock Driver Distribution

UTMC design tools provide methods for balanced clock distri-

bution that maximize drive capability and minimize relative

clock skew between clocked devices.

Speed and Performance

UTMC specializes in high-performance circuits designed to op-

erate in harsh military and radiation environments. Table 3

presents a sampling of typical cell delays.

Note that the propagation delay for a CMOS device is a function

of its fanout loading, supply voltage, operating temperature, and

processing tolerance. In a radiation environment, additional per-

formance variances must be considered. The UTR 0.8µ

simulation models account for all of these effects to accurately

determine circuit performance for its particular set of use

conditions.

Power Dissipation

Each internal gate or I/O driver has an average power consump-

tion based on its switching frequency and capacitive loading.

The radiation-hardened processes exhibit power dissipation that

is typical of CMOS processes. For a rigorous power estimating

methodology, refer to the UTMC UTR 0.8µ Design Manual or

consult with a UTMC Applications Engineer.

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