AV1574BM Просмотр технического описания (PDF) - Integrated Circuit Systems

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AV1574BM

User Programmable Laser Engine Pixel Clock Generator

Integrated Circuit Systems 

ICS1574B

BIT(S)

15

16

17 – 24

25 – 27

28

29 – 30

31

32

33 – 38

39

40

41 – 44

BIT REF.

DESCRIPTION

Reserved

Must be set to 0.

AUX_PCLK

Must be set to 0 except when in the AUX-EN test mode.

When in the AUX-EN test mode, this bit controls the

PCLK output.

Reserved

Must be set to 0.

V[0]..V[2]

Sets the gain of VCO

V[2]

1

1

1

1

V[1]

0

0

1

1

V[0]

0

1

0

1

VCO GAIN

(MHz/Volt)

30

45

60

80

Reserved

P[0]..P[1]

Must be set to 1.

Sets the gain of the phase detector according to this table:

P[1]

P[0]

GAIN (µA/radian)

0

0

0.05

0

1

0.15

1

0

0.5

1

1

1.5

Reserved

P[2]

See text.

M[0]..M[5]

PCLKEN_POL

DBLFREQ

12 /14).

A[0]..A[3]

Must be set to 0.

Phase detector tuning bit. Should normally be set to one.

M counter control bits. Modulus = value + 1.

When = 0, PCLK output enabled when PCLKEN input is

low. When = 1, PCLK output enabled when PCLKEN input

is high.

Doubles modulus of dual-modulus prescaler (from 6 /7 to

Controls A counter. When set to zero, modulus = 7.

Otherwise, modulus = 7 for "value" underflows of the

prescaler, and modulus = 6 thereafter until M counter

underflows.

8

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