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ICS527R-01T

Clock Slicer™ User Configurable Zero Delay Buffer

Integrated Circuit Systems 

ICS527-01

Clock Slicer™

User Configurable Zero Delay Buffer

Electrical Specifications

Parameter

Conditions

Minimum Typical

ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)

Supply Voltage, VDD

Referenced to GND

Inputs

Referenced to GND

-0.5

Clock Output

Referenced to GND

-0.5

Ambient Operating Temperature

ICS527R-01

0

ICS527R-01I

-40

Soldering Temperature

Max of 10 seconds

Storage Temperature

-65

DC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)

Operating Voltage, VDD

3

Input High Voltage, VIH

2

Input Low Voltage, VIL

Input High Voltage, VIH, ICLK and FBIN

pins 7, 8

(VDD/2)+1

Input Low Voltage, VIL, ICLK and FBIN

pins 7, 8

Output High Voltage, VOH (2X DRIVE = 0)

IOH=-12mA

2.4

Output Low Voltage, VOL (2X DRIVE = 0)

IOL=12mA

Output High Voltage, VOH (2X DRIVE = 1)

IOH=-25mA

2.4

Output Low Voltage, VOL (2X DRIVE = 1)

IOL=25mA

IDD Operating Supply Current, 15 MHz IN

60MHz out, no load

8

IDD Operating Supply Current, Power Down

20

Short Circuit Current (2XDRIVE = 0)

CLK outputs

±70

Short Circuit Current (2XDRIVE = 1)

CLK outputs

±140

On-Chip Pull-up Resistor

270

Input Capacitance

4

AC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)

Input Frequency, clock input

0.6

Output Frequency, CLK1

0 C to 70 °C

4

-40 C to +85 °C

4

CLK1 Frequency for correct SYNC operation

Output Clock Rise Time

0.8 to 2.0V

1

Output Clock Fall Time

2.0 to 0.8V

1

Output Clock Duty Cycle

at VDD/2, 15 pF load

45

50

Power Down Time,PDTS low to clocks tri-stated

Power Up Time, PDTS high to clocks stable

Absolute Clock Period Jitter

Deviation from mean

±90

One Sigma Clock Period Jitter

40

Skew of output clocks, CLK1 to CLK2

Note 1

-250

0

Input to output skew, ICLK to FBIN

Note 1

-250

0

Device to device skew, common ICLK

at FBIN

0

Maximum Units

7

V

VDD+0.5 V

VDD+0.5 V

70

°C

85

°C

260

°C

150

°C

3.6

V

V

0.8

V

V

(VDD/2)-1 V

V

0.4

V

V

0.4

V

mA

µA

mA

mA

kΩ

pF

200

MHz

160

MHz

140

MHz

66

MHz

ns

ns

55

%

50

ns

10

ms

ps

ps

250

ps

250

ps

500

ps

Note 1: Assumes clocks with same rise time, measured from rising edges at VDD/2.

MDS 527-01 B

7

Revision 020801

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126•(408)295-9800tel • www.icst.com

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