ADM8690ARN-REEL Просмотр технического описания (PDF) - Analog Devices
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ADM8690ARN-REEL Datasheet PDF : 24 Pages
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Data Sheet
ADM8690/ADM8691/ADM8695
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VOUT 1
VCC 2
GND 3
PFI 4
ADM8690
TOP VIEW
(Not to Scale)
8 VBATT
7 RESET
6 WDI
5 PFO
Figure 3. ADM8690 Pin Configuration,
8-Lead PDIP and 8-Lead SOIC_N
VBATT 1
16 RESET
VOUT 2
15 RESET
VCC 3
GND 4
BATT ON 5
LOW LINE 6
ADM8691/ 14 WDO
ADM8695 13 CEIN
TOP VIEW
(Not to Scale)
12
CEOUT
11 WDI
OSC IN 7
10 PFO
OSC SEL 8
9 PFI
Figure 4. ADM8691/ADM8695 Pin Configuration, 16-Lead PDIP,
16-Lead SOIC_N, 16-Lead SOIC_W, and 16-Lead TSSOP
Table 4. Pin Function Descriptions
Pin No.
8-Lead 16-Lead Mnemonic
8
1
VBATT
1
2
VOUT
2
3
3
4
N/A
5
VCC
GND
BATT ON
N/A
6
N/A
7
LOW LINE
OSC IN
N/A
8
4
9
5
10
6
11
N/A
12
N/A
13
N/A
14
OSC SEL
PFI
PFO
WDI
CEOUT
CEIN
WDO
Description
Backup Battery Input. VBATT or VCC is internally switched to VOUT, depending on which is at the
highest potential.
Output Voltage. VCC or VBATT is internally switched to VOUT, depending on which is at the highest
potential. VOUT can supply up to 100 mA to power CMOS RAM. Connect VOUT to VCC if VOUT and VBATT
are not used.
Power Supply Input. 5 V nominal. VCC or VBATT is internally switched to VOUT, depending on which is
at the highest potential.
Ground. This is the 0 V ground reference for all signals.
Logic Output. BATT ON goes high when VOUT is internally switched to the VBATT input. It goes low
when VOUT is internally switched to VCC. The output typically sinks 35 mA and can directly drive the
base of an external PNP transistor to increase the output current above the 100 mA rating of VOUT.
Logic Output. LOW LINE goes low when VCC falls below the reset threshold. It returns high as
soon as VCC rises above the reset threshold.
Oscillator Logic Input. When OSC SEL is low, OSC IN can be driven by an external clock signal, or
an external capacitor can be connected between OSC IN and GND. This sets both the reset active
pulse timing and the watchdog timeout period (see Table 5 and Figure 17 through Figure 20).
When OSC SEL is high or floating, the internal oscillator is enabled and the reset active time is
fixed at 50 ms typical (ADM8691) or 200 ms typical (ADM8695). In this mode, the OSC IN pin
selects either the fast (100 ms) or slow (1.6 sec) watchdog timeout period. In both modes, the
timeout period immediately after a reset is 1.6 sec typical.
Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal
oscillator sets the reset active time and watchdog timeout period. When OSC SEL is low, the
external oscillator input, OSC IN, is enabled (see Table 5). OSC SEL has a 5 μA internal pull-up.
Power-Fail Input. PFI is the noninverting input to the power-fail comparator. When PFI is less than
1.3 V, PFO goes low. Connect PFI to GND or VOUT when not used.
Power-Fail Output. PFO is the output of the power-fail comparator. It goes low when PFI is less
than 1.3 V. The comparator is turned off and PFO goes low when VCC is below VBATT.
Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than
the watchdog timeout period, RESET pulses low and WDO goes low. The timer is reset with each
transition on the WDI line. The watchdog timer can be disabled if WDI is left floating or is driven
to midsupply.
Logic Output. CEOUT is a gated version of the CEIN signal. CEOUT tracks CEIN when VCC is above the reset
threshold. If VCC is below the reset threshold, CEOUT is forced high. See Figure 21 and Figure 22.
Logic Input. Input to the CE gating circuit. When not in use, connect this pin to GND or VOUT.
Logic Output. The watchdog output, WDO, goes low if WDI remains either high or low for longer
than the watchdog timeout period. WDO is set high by the next transition at WDI. If WDI is
unconnected or at midsupply, the watchdog timer is disabled and WDO remains high. WDO also
goes high when LOW LINE goes low.
Rev. C | Page 7 of 24
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