ISP1581 Просмотр технического описания (PDF) - Philips Electronics

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производитель

ISP1581

Universal serial bus 2.0 high-speed interface device

Philips Electronics 

Philips Semiconductors

ISP1581

USB 2.0 HS interface device

9397 750 09665

Product data

Table 2: Pin description for LQFP64 …continued

Symbol[1]

Pin Type[2] Description

READY/

IORDY

22 I/O

Generic processor mode: ready signal (READY; output)

A LOW level signals that ISP1581 is processing a previous

command or data and is not ready for the next command or

data transfer; a HIGH level signals that ISP1581 is ready

for the next microprocessor read or write.

Split Bus mode: DMA ready signal (IORDY; input); used

for accessing ATA/ATAPI peripherals (PIO and UDMA

modes only).

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

DGND

23 -

digital ground

VCC(3.3)[3]

24 -

supply voltage (3.3 V ± 0.3 V); supplies internal digital

circuits or it is the tapped out voltage from the internal

regulator; this regulated voltage cannot be used to drive

external devices; see Section 10

CS

25 I

chip select input; TTL; 5 V tolerant.

(R/W)/RD

26 I

input; function is determined by input MODE0 at power-up:

DS/WR

27 I

MODE0 = 0 — pin functions as R/W (Motorola style)

MODE0 = 1 — pin functions as RD (8051 style).

input pad; TTL with hysteresis; 5 V tolerant.

input; function is determined by input MODE0 at power-up:

INT

ALE/A0

28 O

29 I

MODE0 = 0 — pin functions as DS (Motorola style)

MODE0 = 1 — pin functions as WR (8051 style).

input pad; TTL with hysteresis; 5 V tolerant.

interrupt output; programmable polarity (active HIGH or

LOW) and signaling (edge or level triggered); CMOS

output; 5 ns slew rate control.

input; function determined by input MODE1 during

power-up:

MODE1 = 0 — pin functions as ALE (address latch

enable); a falling edge latches the address on the

multiplexed address/data bus (AD[7:0])

MODE1 = 1 — pin functions as A0 (address/data selection

on AD[7:0]); a logic 1 detected on the rising edge of the

WR pulse qualifies AD[7:0] as a register address; a logic 0

detected on the rising edge of the WR pulse qualifies

AD[7:0] as a register data; used in Split Bus mode only.

input pad; TTL; 5 V tolerant.

AD0

30 I/O

bit 0 of multiplexed address/data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

AD1

31 I/O

bit 1 of multiplexed address/data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

Rev. 04 — 18 July 2002

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

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