ISP1581 Просмотр технического описания (PDF) - Philips Electronics

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ISP1581

Universal serial bus 2.0 high-speed interface device

Philips Electronics 

Philips Semiconductors

ISP1581

USB 2.0 HS interface device

7. Functional description

The ISP1581 is a high-speed USB device controller. It implements the USB 2.0/1.1

physical layer, the packet protocol layer and maintains up to 16 USB endpoints

concurrently (control IN and control OUT, 7 IN and 7 OUT configurable) along with

Endpoint EP0setup, which is used to access the setup buffer. USB Chapter 9 protocol

handling is executed by means of external firmware.

The ISP1581 has a fast general-purpose interface for communication with most types

of microcontrollers/processors. This Microcontroller Interface is configured by pins

BUS_CONF, MODE1 and MODE0 to accommodate most interface types. Two bus

configurations are available, selected via input BUS_CONF during power-up:

• Generic Processor mode (BUS_CONF = 1):

– AD[7:0]: 8-bit address bus (selects target register)

– DATA[15:0]: 16-bit data bus (shared by processor and DMA)

– Control signals: R/W and DS or RD and WR (selected via pin MODE0), CS

– DMA interface (generic slave mode only): uses lines DATA[15:0] as data bus,

DIOR and DIOW as dedicated read and write strobes.

• Split Bus mode (BUS_CONF = 0):

– AD[7:0]: 8-bit local microprocessor bus (multiplexed address/data)

– DATA[15:0]: 16-bit DMA data bus

– Control signals: CS, ALE or A0 (selected via pin MODE1), R/W and DS or RD

and WR (selected via pin MODE0)

– DMA interface (master or slave mode): uses DIOR and DIOW as dedicated read

and write strobes.

For high-bandwidth data transfer, the integrated DMA handler can be invoked to

transfer data to/from external memory or devices. The DMA Interface can be

configured by writing to the proper DMA registers (see Section 9.4).

The ISP1581 supports high-speed USB 2.0 and full-speed USB 1.1 signaling.

Detection of the USB signaling speed is done automatically.

ISP1581 has 8 kbytes of internal FIFO memory, which is shared among the enabled

USB endpoints.

There are 7 IN endpoints, 7 OUT endpoints and 2 control endpoints that are a fixed

64 bytes long. Any of the 7 IN and 7 OUT endpoints can be separately enabled or

disabled. The endpoint type (interrupt, isochronous or bulk) and packet size of these

endpoints can be individually configured depending on the requirements of the

application. Optional double buffering increases the data throughput of these data

endpoints.

The ISP1581 requires a single supply of 3.3 V or 5.0 V, depending on the I/O voltage.

It has 5.0 V tolerant I/O pads and has an internal 3.3 V regulator for powering the

analog transceiver.

The ISP1581 operates on a 12 MHz crystal oscillator. An integrated 40× PLL clock

multiplier generates the internal sampling clock of 480 MHz.

9397 750 09665

Product data

Rev. 04 — 18 July 2002

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

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