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A16450

Universal Asynchronous Receiver/Transmitter

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a16450 Universal Asynchronous Receiver/Transmitter Data Sheet

Table 7 lists the number of stop bits and word length associated with bit 2.

Table 7. Stop Bit Control Format

Bit 2

0

1

1

1

1

Word Length

Note (1)

X

5 bits

6 bits

7 bits

8 bits

Note:

(1) The X indicates “don’t care.”

Number of Stop Bits

1

1.5

2

2

2

Modem Control Register

The modem control register controls the modem interface outputs.

Table 8 describes the modem control register format.

Table 8. Modem Control Register Format

Bit Signal

Description

0

dtr Data terminal ready. The user can program the dtr bit to control the ndtr output.

1

rts Request to send. The user can program the rts bit to control the nrts output.

2

out1 Output 1. The user can program the out1 bit to control the nout1 output.

3

out2 Output 2. The user can program the out2 bit to control the nout2 output.

4

el Enable loopback. When high, bit 4 causes the following:

s The sout output is set to a logic high.

s The sin input is disconnected (i.e., ignored).

s The output of the transmitter shift register is internally connected (loopbacked) to the

receiver shift register input.

s The modem control inputs are disconnected (i.e., ignored).

s The modem control outputs are used internally in place of the modem control inputs.

7..5

– Not used. These read-only bits are always set to a logic low.

Line Status Register

The line status register enables the host processor to examine data

transfers. Table 9 describes the line status register format.

74

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