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SHM-12L Просмотр технического описания (PDF) - DATEL Data Acquisition products

Номер в каталоге
Компоненты Описание
производитель
SHM-12L
Datel
DATEL Data Acquisition products  Datel
SHM-12L Datasheet PDF : 6 Pages
1 2 3 4 5 6
SHM-12
®
®
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
LIMITS
UNITS
+5V Supply
0 to +6
Volts
–5V Supply
0 to –6
Volts
Analog Input
+5V Supply –1
Volts
–5V Supply +1
Volts
Continuous Output Current
±50
mA
Digital Inputs
<Supply Voltages
Volts
Junction Temperature
+175
°C
Lead Temperature (10 seconds)
+300
°C
Output shorted to any supply will cause permanent damage.
FUNCTIONAL SPECIFICATIONS
(Apply over the operating temperature range using a 100resistive load, 10pF
capacitive load, ECL digital input levels, a 47pF external hold capacitor, and ±5V
nominal supplies, unless otherwise specified.)
INPUTS
Input Voltage Range
Input Impedance
Digitals Inputs (Balanced ECL)
Logic Levels
Logic 1
Logic 0
Logic Loading
Logic 1
Logic 0
OUTPUTS
Output Voltage Range
Output Current
Output Impedance (dc)
Stable Capacitive Load
MIN.
–1.5
0.3
TYP.
1
MAX. UNITS
+1.5 Volts
M
–1.5 — +1.8 Volts
–2.5 — +0.8 Volts
— +10 +50 µ A
— –30 –150 µ A
–1.5 — +1.5 Volts
± 30 —
mA
0.3
1
50
pF
PERFORMANCE
Nonlinearity (±1V)
+25°C
–40 to +85°C
–55 to +125°C
Sample Mode Offset
+25°C
–40 to +85°C
–55 to +125°C
Pedestal
+25°C
–40 to +85°C
–55 to +125°C
Gain, +25°C
Gain Drift (±1V)
–40 to +85°C
–55 to +125°C
Aperture Delay
–40 to +85°C
–55 to +125°C
Aperture Jitter
–40 to +85°C
–55 to +125°C
Harmonic Distortion (±1V)
dc to 1MHz
dc to 10MHz
+25°C
–40 to +85°C
–55 to +125°C
Acquisition Time (±0.012%, ±1V)
–40 to +85°C
–55 to +125°C
Acquisition Time (±0.024%, ±1V)
–40 to +85°C
–55 to +125°C
Acquisition Time (±0.05%, ±1V)
–40 to +85°C
–55 to +125°C
— ±0.006 —
%
— ±0.024 %
— ±0.024 %
±12
mV
— ±20 mV
— ±30 mV
±3
mV
— ±20 mV
— ±20 mV
+0.98 +0.995 —
V/V
— ±20 ppm/°C
— ±30 ppm/°C
2
ns
2
ns
1
— ps rms
1
— ps rms
–75
dB
–62
dB
— –56 dB
— –54 dB
20
ns
30
ns
15
30
ns
25
40
ns
12
25
ns
15
30
ns
PERFORMANCE (Cont.)
Acquisition Time (±0.1%, ±1V)
–40 to +85°C
–55 to +125°C
Hold Mode Settling (±0.012%)
–40 to +85°C
–55 to +125°C
Hold Mode Settling (±0.024%)
–40 to +85°C
–55 to +125°C
Hold Mode Settling (±0.05%)
–40 to +85°C
–55 to +125°C
Hold Mode Settling (±0.1%)
–40 to +85°C
–55 to +125°C
Slew Rate
Full Power Bandwidth (±1V)
Small Signal Bandwidth
Output Noise, Hold Mode
Feedthrough (2V Step)
Droop Rate
+25°C
–40 to +85°C
–55 to +125°C
MIN. TYP. MAX. UNITS
10
20
ns
10
20
ns
10
ns
10
ns
7
18
ns
7
18
ns
6
15
ns
6
15
ns
5
12
ns
5
12
ns
±220 ±350 —
V/µs
35
55
MHz
50
120
MHz
65
— µVrms
–80
dB
— ±0.5 ±1.5 mV/µs
±2
±5 mV/µs
— ±2.5 ±10 mV/µs
POWER SUPPLY REQUIREMENTS
Power Supply Range
+5V Supply
–5V Supply
Power Supply Current
+5V Supply
–5V Supply
Power Dissipation
Power Supply Rejection Ratio
+4.5 +5 +5.5 Volts
–5.5 –5 –4.5 Volts
+17 +25 +30
mA
–17 –25 –30
mA
170 250 300 mW
40
60
dB
ENVIRONMENTAL
Operating Temp. Range, Case
SHM-12S, SHM-12L
SHM-12LM
Storage Temperature Range
Package Type
SHM-12S
SHM-12L, SHM-12LM
–40 — +85
°C
–55 — +125 °C
–65 — +150 °C
20-Pin plastic SOIC
20-Pin ceramic LCC
Footnotes:
Short circuit protection at ±50mA.
TECHNICAL NOTES
The SHM-12 employs an open loop architecture to achieve its
superior high-speed characteristics. The first stage buffer
amplifier incorporates the sample-and-hold switch. This allows
for a fast acquisition time which is not limited by slew current
like the traditional Schottky diode bridge switch. The output
amplifier uses a closed loop voltage feedback design which
provides a low (0.3, typical) output impedance. Gain and
linearity are not affected by heavy loads.
The design has been optimized to achieve the high accuracy
associated with fast transient responses over the military tem-
perature range. During the track-to-hold transient, the integral
nonlinearity is not affected and the pedestal remains constant
over the full ±1.5V input range.
An innovative circuit design ensures an extremely low droop rate.
An external hold capacitor can be added to the 15pF internal
hold capacitor to obtain a lower droop rate (the droop rate is pro-
portional to the inverse of the total hold capacitor value) without
increasing transient response times by more than a few ns. The
external hold capacitor should not exceed 100pF.
2

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