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74HCT4353D

Triple 2-channel analog multiplexer/demultiplexer with latch

Philips Electronics 

Philips Semiconductors

Triple 2-channel analog

multiplexer/demultiplexer with latch

Product specification

74HC/HCT4353

FEATURES

• Wide analog input voltage range: ± 5 V

• Low “ON” resistance:

80 Ω (typ.) at VCC − VEE = 4.5 V

70 Ω (typ.) at VCC − VEE = 6.0 V

60 Ω (typ.) at VCC − VEE = 9.0 V

• Logic level translation:

to enable 5 V logic to communicate with ± 5 V analog

signals

• Typical “break before make” built in

• Address latches provided

• Output capability: non-standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT4353 are high-speed Si-gate CMOS

devices. They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT4353 are triple 2-channel analog

multiplexers/demultiplexers with two common enable

inputs (E1 and E2) and a latch enable input (LE). Each

multiplexer has two independent inputs/outputs (nY0 and

nY1), a common input/output (nZ) and select inputs (S1 to

S3).

Each multiplexer/demultiplexer contains two bidirectional

analog switches, each with one side connected to an

independent input/output (nY0 and nY1) and the other side

connected to a common input/output (nZ).

With E1 LOW and E2 HIGH, one of the two switches is

selected (low impedance ON-state) by S1 to S3.

The data at the select inputs may be latched by using the

active LOW latch enable input (LE). When LE is HIGH, the

latch is transparent. When either of the two enable inputs,

E1 (active LOW) and E2 (active HIGH), is inactive, all

analog switches are turned off.

VCC and GND are the supply voltage pins for the digital

control inputs (S1 to S3, LE, E1 and E2). The VCC to GND

ranges are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT.

The analog inputs/outputs (nY0 and nY1, and nZ) can

swing between VCC as a positive limit and VEE as a

negative limit. VCC − VEE may not exceed 10.0 V.

For operation as a digital multiplexer/demultiplexer, VEE is

connected to GND (typically ground).

QUICK REFERENCE DATA

VEE = GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

SYMBOL

PARAMETER

tPZH/ tPZL

tPHZ/ tPLZ

CI

CPD

CS

turn “ON” time E1, E2 or Sn to Vos

turn “OFF” time E1, E2 or Sn to Vos

input capacitance

power dissipation capacitance per switch

max. switch capacitance

independent (Y)

common (Z)

Notes

1. CPD is used to determine the dynamic power

dissipation (PD in µW):

PD =

CPD × VCC2 × fi + ∑ {(CL + CS) × VCC2 × fo} where:

fi = input frequency in MHz

CL = output load capacitance in pF

fo = output frequency in MHz

CS = max. switch capacitance in pF

CONDITIONS

CL = 50 pF; RL = 1 kΩ;

VCC = 5 V

notes 1 and 2

TYPICAL

HC

29

20

3.5

23

HCT

21

22

3.5

23

UNIT

ns

ns

pF

pF

5

5

pF

8

8

pF

∑ {(CL ×CS) × VCC2 × fo} = sum of outputs

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC − 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package

Information”.

December 1990

2

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