SPT7853SCT Просмотр технического описания (PDF) - Signal Processing Technologies
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SPT7853SCT Datasheet PDF : 10 Pages
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ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
VDD .................................................................................................... +6 V
OVDD ................................................................................................. +6 V
Temperature
Analog Inputs .................................. –0.5 V to VDD +0.5 V
VREF ................................................ –0.5 V to VDD +0.5 V
Clock Input ...................................... –0.5 V to VDD +0.5 V
Output Currents
Digital Outputs ....................................................... 10 mA
Temperature
Operating Temperature ................................ 0 to + 70 °C
Junction Temperature ......................................... +150 °C
Lead, Soldering (10 seconds) ............................. +300 °C
Storage .................................................... –65 to +150 °C
Note: 1. Operation at any Absolute Maximum Rating is not implied and operation beyond the ratings may cause damage to the device.
See Electrical Specifications for proper nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, VDD=OVDD=+5.0 V, VIN=0 to 4 V, ƒS=30 MSPS, ƒCLK=60 MHz, VRHS=4.0 V, VRLS=0.0 V, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
SPT7853
MIN
TYP
MAX
UNITS
DC Performance
Resolution
Differential Linearity
Integral Linearity
ƒs = 20 MSPS
V
ƒs = 20 MSPS
V
10
Bits
±0.5
LSB
±1.0
LSB
Analog Input
Input Voltage Range2
Input Resistance
Input Capacitance
Input Bandwidth (Full Power)
–Full-Scale Error2
+Full-Scale Error2
Reference Ladder Resistance
IV
VRLS
VRHS V
IV
50
kΩ
V
5
pF
V
120
MHz
V
±0.5
%FS
V
±0.25
%FS
VI
120
170
220 Ω
Timing Characteristics
Conversion Rate
Clock Duty Cycle Range
Clock-to-Sample Rate Relationship
Pipeline Delay (Latency)
Aperture Delay Time
Aperture Jitter Time
VI
30
MSPS
IV
45
55 %
IV
2:1
IV
12
Clock Cycles
V
5
ns
V
15
ps
Dynamic Performance
Effective Number of Bits
ƒIN = 3.58 MHz
@ 25 °C
VI
8.3
8.7
Bits
@ 0 to 70 °C
V
8.0
Bits
ƒIN = 10.0 MHz
@ 25 °C
V
7.4
Bits
Signal-to-Noise Ratio
ƒIN = 3.58 MHz
@ 25 °C
VI
53
56
dB
@ 0 to 70 °C
V
51.6
dB
ƒIN = 10.0 MHz
@ 25 °C
V
48
dB
Total Harmonic Distortion
ƒIN = 3.58 MHz
@ 25 °C
VI
–56
–58
dB
@ 0 to 70 °C
V
–54.6
dB
ƒIN = 10.0 MHz
@ 25 °C
V
–51
dB
Signal-to-Noise + Distortion Ratio
ƒIN = 3.58 MHz
@ 25 °C
VI
52
54.5
dB
@ 0 to 70 °C
V
49.7
dB
ƒIN = 10.0 MHz
@ 25 °C
V
46
dB
2The full-scale range spans the reference ladder sense pins, VRHS and VRLS. Refer to the Voltage Reference section for discussion.
SPT
2
SPT7853
12/14/99
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