HI5905N/QML Просмотр технического описания (PDF) - Intersil
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HI5905N/QML Datasheet PDF : 8 Pages
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Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
NAME
NC
NC
DGND1
NC
AVCC
AGND
NC
NC
VIN+
VIN-
VDC
NC
VROUT
VRIN
AGND
AVCC
NC
D13
D12
D11
D10
NC
NC
D9
D8
DGND2
DVCC2
NC
D7
D6
D5
D4
D3
NC
NC
D2
D1
D0
NC
CLK
DVCC1
DGND1
DVCC1
NC
DESCRIPTION
No Connection
No Connection
Digital Ground
No Connection
Analog Supply (5.0V)
Analog Ground
No Connection
No Connection
Positive Analog Input
Negative Analog Input
DC Bias Voltage Output
No Connection
Reference Voltage Output
Reference Voltage Input
Analog Ground
Analog Supply (5.0V)
No Connection
Data Bit 11 Output (MSB)
Data Bit 11 Output
Data Bit 11 Output
Data Bit 10 Output
No Connection
No Connection
Data Bit 9 Output
Data Bit 8 Output
Digital Ground
Digital Supply (5.0V)
No Connection
Data Bit 7 Output
Data Bit 6 Output
Data Bit 5 Output
Data Bit 4 Output
Data Bit 3 Output
No Connection
No Connection
Data Bit 2 Output
Data Bit 1 Output
Data Bit 0 Output (LSB)
No Connection
Input Clock
Digital Supply (5.0V)
Digital Ground
Digital Supply (5.0V)
No Connection
4-4
Detailed Description
Theory of Operation
The HI5905 is a 14-bit fully differential sampling pipeline A/D
converter with digital error correction. Figure 3 depicts the
circuit for the front end differential-in-differential-out sample-
and-hold (S/H). The switches are controlled by an internal
clock which is a non-overlapping two phase signal, φ1 and
φ2, derived from the master clock. During the sampling
phase, φ1, the input signal is applied to the sampling
capacitors, CS. At the same time the holding capacitors, CH,
are discharged to analog ground. At the falling edge of φ1
the input signal is sampled on the bottom plates of the
sampling capacitors. In the next clock phase, φ2, the two
bottom plates of the sampling capacitors are connected
together and the holding capacitors are switched to the op
amp output nodes. The charge then redistributes between
CS and CH completing one sample-and-hold cycle. The
output is a fully-differential, sampled-data representation of
the analog input. The circuit not only performs the sample-
and-hold function but will also convert a single-ended input
to a fully-differential output for the converter core. During the
sampling phase, the VIN pins see only the on-resistance of a
switch and CS. The relatively small values of these
components result in a typical full power input bandwidth of
100MHz for the converter.
φ 1 CH
VIN +
φ1
CS
-+
φ2
+-
VIN -
φ1
CS
φ1
CH
φ1
VOUT +
VOUT-
φ1
FIGURE 3. ANALOG INPUT SAMPLE-AND-HOLD
As illustrated in the functional block diagram and the timing
diagram in Figure 1, four identical pipeline subconverter
stages, each containing a four-bit flash converter, a four-bit
digital-to-analog converter and an amplifier with a voltage
gain of 8, follow the S/H circuit with the fifth stage being only
a 4-bit flash converter. Each converter stage in the pipeline
will be sampling in one phase and amplifying in the other
clock phase. Each individual sub-converter clock signal is
offset by 180 degrees from the previous stage clock signal,
with the result that alternate stages in the pipeline will
perform the same operation.
The output of each of the four-bit subconverter stages is a
four-bit digital word containing a supplementary bit to be
used by the digital error correction logic. The output of each
subconverter stage is input to a digital delay line which is
controlled by the internal sampling clock. The function of the
digital delay line is to time align the digital outputs of the four
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