HI5905N/QML Просмотр технического описания (PDF) - Intersil
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HI5905N/QML Datasheet PDF : 8 Pages
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Timing Waveforms
ANALOG
INPUT
CLOCK
INPUT SN - 1 HN - 1 SN
HN SN + 1 HN + 1 SN + 2 HN + 2 SN + 3 HN + 3 SN + 4 HN + 4 SN + 5 HN + 5 SN + 6 HN + 6
INPUT
S/H
1ST
STAGE
B1, N - 1
B1, N
B1, N + 1
B1, N + 2
B1, N + 3
B1, N + 4
B1, N + 5
2ND
STAGE
3RD
STAGE
4TH
STAGE
B2, N - 2
B2, N - 1
B2, N
B2, N + 1
B2, N + 2
B2, N + 3
B2, N + 4
B3, N - 2
B3 , N - 1
B3, N
B3, N + 1
B3, N + 2
B3, N + 3
B3, N + 4
B4, N - 3
B4, N - 2
B4, N - 1
B4, N
B4, N + 1
B4, N + 2
B4, N + 3
5TH
STAGE
DATA
OUTPUT
B5, N - 3
DN - 4
NOTES:
1. SN: N-th sampling period.
2. HN: N-th holding period.
B5, N - 2
B5, N - 1
B5, N
B5, N + 1
B5, N + 2
B5, N + 3
DN - 3
DN - 2
DN - 1
DN
DN + 1
DN + 2
tLAT
3. BM, N: M-th stage digital output corresponding to N-th sampled input.
4. DN: Final data output corresponding to N-th sampled input.
FIGURE 1. INTERNAL CIRCUIT TIMING
ANALOG
INPUT
tAP
tAJ
CLOCK
INPUT
1.5V
1.5V
tOD
tH
DATA
OUTPUT
DATA N-1
3.5V
1.5V
DATA N
FIGURE 2. INPUT-TO-OUTPUT TIMING
4-3
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