EVAL-AD7851CB(RevA) Просмотр технического описания (PDF) - Analog Devices
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EVAL-AD7851CB Datasheet PDF : 36 Pages
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AD7851
Pin Mnemonic
1 CONVST
2 BUSY
3 SLEEP
4
REFIN/
REFOUT
5
AVDD
6, 12 AGND
7
CREF1
8
CREF2
9 AIN(+)
10 AIN(–)
11 NC
13 AMODE
14 POLARITY
15 SM1
16 SM2
17 CAL
18 DVDD
19 DGND
20 DOUT
21 DIN
22 CLKIN
23 SCLK
24 SYNC
Description
PIN FUNCTION DESCRIPTION
Convert Start. Logic input. A low to high transition on this input puts the track/hold into its hold mode and
starts conversion. When this input is not used, it should be tied to DVDD.
Busy Output. The busy output is triggered high by the falling edge of CONVST or rising edge of CAL, and
remains high until conversion is completed. BUSY is also used to indicate when the AD7851 has completed
its on-chip calibration sequence.
Sleep Input/Low Power Mode. A logic 0 initiates a sleep and all circuitry is powered down including the in-
ternal voltage reference provided there is no conversion or calibration being performed. Calibration data is
retained. A logic 1 results in normal operation. See Power-Down section for more details.
Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the
reference source for the analog-to-digital converter. The nominal reference voltage is 4.096 V and this ap-
pears at the pin. This pin can be overdriven by an external reference or can be taken as high as AVDD.
When this pin is tied to AVDD, then the CREF1 pin should also be tied to AVDD.
Analog Positive Supply Voltage, +5.0 V ± 5%.
Analog Ground. Ground reference for track/hold, reference and DAC.
Reference Capacitor (0.01 µF ceramic disc in parallel with a 470 nF NPO type). This external capacitor is
used as a charge source for the internal DAC. The capacitor should be tied between the pin and AGND.
Reference Capacitor (0.01 µF ceramic disc in parallel with a 470 nF NPO type). This external capacitor is
used in conjunction with the on-chip reference. The capacitor should be tied between the pin and AGND.
Analog Input. Positive input of the pseudo-differential analog input. Cannot go below AGND or above
AVDD at any time, and cannot go below AIN(–) when the unipolar input range is selected.
Analog Input. Negative input of the pseudo-differential analog input. Cannot go below AGND or above
AVDD at any time.
No Connect Pin.
Analog Mode Pin. This pin allows two different analog input ranges to be selected. A logic 0 selects range 0
to VREF (i.e., AIN(+) – AIN(–) = 0 to VREF). In this case AIN(+) cannot go below AIN(–) and
AIN(–) cannot go below AGND. A logic 1 selects range –VREF/2 to +VREF/2 (i.e., AIN(+) – AIN(–) =
–VREF /2 to +VREF/2). In this case AIN(+) cannot go below AGND so that AIN(–) needs to be biased to
+VREF/2 to allow AIN(+) to go from 0 V to +VREF V.
Serial Clock Polarity. This pin determines the active edge of the serial clock (SCLK). Toggling this pin will
reverse the active edge of the serial clock (SCLK). A logic 1 means that the serial clock (SCLK) idles high
and a logic 0 means that the serial clock (SCLK) idles low. It is best to refer to the timing diagrams and
Table X for the SCLK active edges.
Serial Mode Select Pin. This pin is used in conjunction with the SM2 pin to give different modes of opera-
tion as described in Table XI.
Serial Mode Select Pin. This pin is used in conjunction with the SM1 pin to give different modes of opera-
tion as described in Table XI.
Calibration Input. This pin has an internal pull-up current source of 0.15 µA. A logic 0 on this pin resets all
logic and initiates a calibration on its rising edge. There is the option of connecting a 10 nF capacitor from
this pin to AGND to allow for an automatic self calibration on power-up. This input overrides all other
internal operations.
Digital Supply Voltage, +5.0 V ± 5%.
Digital Ground. Ground reference point for digital circuitry.
Serial Data Output. The data output is supplied to this pin as a 16-bit serial word.
Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can act
as an input pin or as a I/O pin depending on the serial interface mode the part is in (see Table XI).
Master Clock Signal for the device (6 MHz or 7 MHz). Sets the conversion and calibration times.
Serial Port Clock. Logic input/output. The SCLK pin is configured as an input or output, dependent on the
type of serial data transmission (self-clocking or external-clocking) that has been selected by the SM1 and
SM2 pins. The SCLK idles high or low depending on the state of the POLARITY pin.
This pin can be an input level triggered active low (similar to a chip select in one case and to a frame sync
in the other) or an output (similar to a frame sync) pin depending on SM1, SM2 (see Table XI).
–8–
REV. A
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