EVAL-AD7851CB(RevA) Просмотр технического описания (PDF) - Analog Devices
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EVAL-AD7851CB Datasheet PDF : 36 Pages
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TYPICAL TIMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams.
Figure 2 shows the reading and writing after conversion in In-
terface Modes 2 and 3. To attain the maximum sample rate of
285 kHz in Interface Modes 2 and 3, reading and writing must
be performed during conversion. Figure 3 shows the timing dia-
gram for Interface Modes 4 and 5 with sample rate of 285 kHz.
At least 330 ns acquisition time must be allowed (the time from
the falling edge of BUSY to the next rising edge of CONVST)
before the next conversion begins to ensure that the part is
settled to the 14-bit level. If the user does not want to provide
the CONVST signal, the conversion can be initiated in software
by writing to the control register.
AD7851
1.6mA IOL
TO
OUTPUT
PIN
CL
50pF
200µA
IOH
+2.1V
Figure 1. Load Circuit for Digital Output Timing
Specifications
POLARITY PIN LOGIC HIGH
t1
CONVST (I/P)
t2
BUSY (O/P)
tCONVERT
tCONVERT = 3.25µs MAX, t1 = 100ns MIN,
t5 = 30ns MAX, t7 = 30ns MIN
SYNC (I/P)
SCLK (I/P)
DOUT (O/P)
DIN (I/P)
t5
3-STATE
t3
1
t6
DB15
t7
t8
DB15
t9
5
6
t10
t6
DB11
DB11
t11
16
t12
DB0
3-STATE
DB0
Figure 2. AD7851 Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3)
POLARITY PIN LOGIC HIGH
t1
CONVST (I/P)
t2
BUSY (O/P)
tCONVERT = 3.25µs MAX, t1 = 100ns MIN,
t5 = 30ns MAX, t7 = 30ns MIN
tCONVERT
SYNC (O/P)
SCLK (O/P)
DOUT (O/P)
DIN (I/P)
t4
1
t5
3-STATE
DB15
t7
t8
DB15
5
t6
t9
6
t10
DB11
t11
16
DB0
t12
3-STATE
DB11
DB0
Figure 3. AD7851 Timing Diagram (Typical Read and Write Operation for Interface Modes 4, 5)
REV. A
–5–
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