EVAL-AD7851CB(RevA) Просмотр технического описания (PDF) - Analog Devices
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EVAL-AD7851CB Datasheet PDF : 36 Pages
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AD7851
TIMING SPECIFICATIONS1 (AVDD = DVDD = +5.0 V ؎ 5%; fCLKIN = 6 MHz, TA = TMIN to TMAX, unless otherwise noted)
Parameter
Limit at TMIN, TMAX
A, K
Units
Description
fCLKIN2
fSCLK3
t14
t2
tCONVERT
t3
t4
t55
t5A5
t65
t7
t8
t96
t106
t11
t11A
t127
t13
t148
t15
t16
tCAL9
tCAL19
tCAL29
tDELAY
500
7
10
fCLK IN
100
50
3.25
–0.4 tSCLK
± 0.4 tSCLK
0.6 tSCLK
30
30
45
30
20
0.4 tSCLK
0.4 tSCLK
30
30/0.4 tSCLK
50
50
90
50
2.5 tCLKIN
2.5 tCLKIN
41.7
37.04
4.63
65
kHz min
MHz max
MHz max
MHz max
ns min
ns max
µs max
ns min
ns min/max
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min/max
ns max
ns max
ns max
ns max
ns max
ns max
ms typ
ms typ
ms typ
ns max
Master Clock Frequency
Interface Modes 1, 2, 3 (External Serial Clock)
Interface Modes 4, 5 (Internal Serial Clock)
CONVST Pulse Width
CONVST↓ to BUSY↑ Propagation Delay
Conversion Time = 20 tCLKIN
SYNC↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input)
SYNC↓ to SCLK↓ Setup Time (Continuous SCLK Input)
SYNC↓ to SCLK↓ Setup Time. Interface Mode 4 Only
Delay from SYNC↓ until DOUT 3-State Disabled
Delay from SYNC↓ until DIN 3-State Disabled
Data Access Time After SCLK↓
Data Setup Time Prior to SCLK↑
Data Valid to SCLK Hold Time
SCLK High Pulse Width (Interface Modes 4 and 5)
SCLK Low Pulse Width (Interface Modes 4 and 5)
SCLK↑ to SYNC↑ Hold Time (Noncontinuous SCLK)
(Continuous SCLK) Does Not Apply to Interface Mode 3
SCLK↑ to SYNC↑ Hold Time
Delay from SYNC↑ until DOUT 3-State Enabled
Delay from SCLK↑ to DIN Being Configured as Output
Delay from SCLK↑ to DIN Being Configured as Input
CAL↑ to BUSY↑ Delay
CONVST↓ to BUSY↑ Delay in Calibration Sequence
Full Self-Calibration Time, Master Clock Dependent (250026
tCLKIN)
Internal DAC Plus System Full-Scale Cal Time, Master Clock
Dependent (222228 tCLKIN)
System Offset Calibration Time, Master Clock Dependent
(27798 tCLKIN)
Delay from CLK to SCLK
NOTES
Descriptions that refer to SCLK↑ (rising) or SCLK↓ (falling) edges here are with the POLARITY pin HIGH. For the POLARITY pin LOW then the opposite edge of
SCLK will apply.
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. See
Table X and timing diagrams for different interface modes and calibration.
2Mark/Space ratio for the master clock input is 40/60 to 60/40.
3For Interface Modes 1, 2, 3 the SCLK max frequency will be 10 MHz. For Interface Modes 4 and 5 the SCLK will be an output and the frequency will be f CLKIN.
4The CONVST pulse width will here only apply for normal operation. When the part is in power-down mode, a different CONVST pulse width will apply (see Power-
Down section).
5Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
6For self-clocking mode (Interface Modes 4, 5) the nominal SCLK high and low times will be 0.5 t SCLK = 0.5 tCLKIN.
7t12 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 12, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
8t14 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true delay of the part in
turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line knowing that a bus conflict will
not occur.
9The typical time specified for the calibration times is for a master clock of 6 MHz.
Specifications subject to change without notice.
–4–
REV. A
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