EVAL-AD7854CB Просмотр технического описания (PDF) - Analog Devices
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EVAL-AD7854CB Datasheet PDF : 28 Pages
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AD7854/AD7854L
Parameter
A Version1 B Version1 S Version1 Units
Test Conditions/Comments
POWER REQUIREMENTS
AVDD, DVDD
IDD
Normal Mode5
Sleep Mode6
With External Clock On
With External Clock Off
Normal Mode Power Dissipation
Sleep Mode Power Dissipation
With External Clock On
With External Clock Off
+3.0/+5.5
5.5 (1.8)
5.5 (1.8)
10
400
5
200
30 (10)
20 (6.5)
55
36
27.5
18
+3.0/+5.5
5.5 (1.8)
5.5 (1.8)
10
400
5
200
30 (10)
20 (6.5)
55
36
27.5
18
+3.0/+5.5 V min/max
6 (1.8)
6 (1.8)
mA max
mA max
AVDD = DVDD = 4.5 V to 5.5 V. Typically 4.5 mA
(1.5 mA);
AVDD = DVDD = 3.0 V to 3.6 V. Typically 4.0 mA
(1.5 mA).
10
400
5
200
30 (10)
20 (6.5)
55
36
27.5
18
µA typ
µA typ
µA max
µA typ
mW max
mW max
µW typ
µW typ
µW max
µW max
Full power-down. Power management bits in control
register set as PMGT1 = 1, PMGT0 = 0.
Partial power-down. Power management bits in
control register set as PMGT1 = 1, PMGT0 = 1.
Typically 1 µA. Full power-down. Power management
bits in control register set as PMGT1 = 1,
PMGT0 = 0.
Partial power-down. Power management bits in
control register set as PMGT1 = 1, PMGT0 = 1.
VDD = 5.5 V: Typically 25 mW (8)
VDD = 3.6 V: Typically 15 mW (5.4)
VDD = 5.5 V
VDD = 3.6 V
VDD = 5.5 V: Typically 5.5 µW
VDD = 3.6 V: Typically 3.6 µW
SYSTEM CALIBRATION
Offset Calibration Span7
Gain Calibration Span7
+0.05 × VREF/–0.05 × VREF
+0.025 × VREF/–0.025 × VREF
V max/min Allowable Offset Voltage Span for Calibration
V max/min Allowable Full-Scale Voltage Span for Calibration
NOTES
1Temperature ranges as follows: A, B Versions, –40°C to +85°C; S Version, –55°C to +125°C.
2Specifications apply after calibration.
3Not production tested. Guaranteed by characterization at initial product release.
4Sample tested @ +25°C to ensure compliance.
5All digital inputs @ DGND except for CONVST @ DVDD. No load on the digital outputs. Analog inputs @ AGND.
6CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST @ DVDD. No load on the digital outputs. Analog inputs @ AGND.
7The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7854/AD7854L can calibrate. Note also that these are voltage spans
and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ± 0.05 × VREF,
and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be VREF ± 0.025 × VREF
(unipolar mode) and VREF/2 ± 0.025 × VREF (bipolar mode)). This is explained in more detail in the calibration section of the data sheet.
Specifications subject to change without notice.
REV. B
–3–
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