HI5960IAZ-T Просмотр технического описания (PDF) - Intersil

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HI5960IAZ-T

14-Bit, 130MSPS, High Speed D/A Converter

Intersil 

HI5960

Pin Descriptions

PIN NO.

PIN NAME

DESCRIPTION

1-14

15

16

17

18

19

21

22

23

24

20, 25

26

27

28

D13 (MSB) Through Digital Data Bit 13, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).

D0 (LSB)

SLEEP

Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep

pin has internal 20µA active pulldown current.

REFLO

Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal

reference.

REFIO

Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is

enabled. Use 0.1µF cap to ground when internal reference is enabled.

FSADJ

COMP1

IOUTB

Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output

Current = 32 x VFSADJ/RSET.

For use in reducing bandwidth/noise. Recommended: connect 0.1µF to AVDD.

The complimentary current output of the device. Full scale output current is achieved when all input bits

are set to binary 0.

IOUTA

Current output of the device. Full scale output current is achieved when all input bits are set to binary 1.

COMP2

Connect 0.1µF capacitor to ACOM.

AVDD

ACOM

Analog Supply (+3V to +5V).

Connect to Analog Ground.

DCOM

Connect to Digital Ground.

DVDD

CLK

Digital Supply (+3V to +5V).

Clock Input. Input data to the DAC passes through the “master” latches when the clock is low and is

latched into the “master” latches when the clock is high. Data presented to the “slave” latch passes

through when the clock is logic high and is latched into the “slave” latches when the clock is logic low.

Adequate setup time must be allowed for the MSBs to pass through the thermometer decoder before the

clock goes high. This master-slave arrangement comprises an edge-triggered flip-flop, with the DAC

being updated on the rising clock edge. It is recommended that the clock edge be skewed such that setup

time is larger than the hold time.

3

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