HI5960IAZ Просмотр технического описания (PDF) - Intersil

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производитель

HI5960IAZ

14-Bit, 130MSPS, High Speed D/A Converter

Intersil 

Timing Diagrams

HI5960

CLK

50%

D13-D0

IOUT

ERROR BAND

tSETT

tPD

FIGURE 2. OUTPUT SETTLING TIME DIAGRAM

V

GLITCH AREA = 1/2 (H x W)

HEIGHT (H)

WIDTH (W)

t (ps)

FIGURE 3. PEAK GLITCH AREA (SINGLET) MEASUREMENT

METHOD

CLK

D13-D0

IOUT

tPW1

tPW2

tSU

tSU

tSU

tHLD

tHLD

tHLD

50%

tPD

tSETT

tPD

tSETT

tPD

tSETT

FIGURE 4. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM

10

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