HI5741 Просмотр технического описания (PDF) - Intersil

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Компоненты Описание

производитель

HI5741

14-Bit, 100MSPS, High Speed D/A Converter

Intersil 

HI5741

Absolute Maximum ratings TA = +25°C

Digital Supply Voltage VCC to DGND . . . . . . . . . . . . . . . . . . . +5.5V

Negative Digital Supply Voltage DVEE to DGND . . . . . . . . . . -5.5V

Negative Analog Supply Voltage AVEE to AGND, ARTN . . . . -5.5V

Digital Input Voltages (D13-D0, CLK) to DGND. . . . . DVCC to -0.5V

Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . ±2.5mA

Voltage from CTRL AMP IN to AVEE. . . . . . . . . . . . . . . . 2.5V to 0V

Control Amplifier Output Current . . . . . . . . . . . . . . . . . . . . . ±2.5mA

Reference Input Voltage Range. . . . . . . . . . . . . . . . . -3.7V to AVEE

Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Thermal Information

Thermal Resistance (Typical, Note 1)

θJA (°C/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . .

70

Maximum Junction Temperature

HI5741BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range . . . . . . . . .-65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Electrical Specifications AVEE, DVEE = -4.94V to -5.46V, VCC = +4.75 to +5.25V, VREF = Internal,

TA = +25°C

PARAMETER

TEST CONDITIONS

HI5741BI

TA = -40°C TO +85°C

MIN TYP MAX

SYSTEM PERFORMANCE

Resolution

14

-

-

Integral Linearity Error, INL

(Note 5)

Differential Linearity Error, DNL

Offset Error, IOS

Full Scale Gain Error, FSE

“Best Fit Straight Line”, TA = +25°C

“Best Fit Straight Line”, TA = -40°C to +85°C

(Note 5) TA = +25°C

(Note 5)

(Notes 3, 5)

-1.5 ±1.0 1.5

-1.75

-

1.75

-1.0 ±0.5 1.0

-

8

75

-

3.2

10

Full Scale Gain Drift

With Internal Reference

-

±150

-

Offset Drift Coefficient

Full Scale Output Current, IFS

Output Voltage Compliance Range

DYNAMIC CHARACTERISTICS

Throughput Rate

Output Voltage Settling Time

(1/16th Scale Step Across Segment)

Singlet Glitch Area, GE (Peak)

Output Slew Rate

Output Rise Time

Output Fall Time

Spurious Free Dynamic Range within a Window

(Note 4)

(Note 4)

(Note 4)

(Note 4)

RL = 64Ω (Note 4) - Settling to 0.024%

RL = 64Ω (Note 4) - Settling to 0.012%

RL = 64Ω (Note 4)

RL = 64Ω, DAC Operating in Latched Mode (Note 4)

RL = 64Ω, DAC Operating in Latched Mode (Note 4)

RL = 64Ω, DAC Operating in Latched Mode (Note 4)

fCLK = 10 MSPS, fOUT = 1.23MHz, 2MHz Span

fCLK = 20 MSPS, fOUT = 5.055MHz, 2MHz Span

fCLK = 40 MSPS, fOUT = 16MHz, 10MHz Span

fCLK = 50 MSPS, fOUT = 10.1MHz, 2MHz Span

fCLK = 80 MSPS, fOUT = 5.1MHz, 2MHz Span

fCLK = 100 MSPS, fOUT = 10.1MHz, 2MHz Span

-

-

0.05

- -20.48 -

-1.25

-

0

100

-

-

-

11

-

-

20

-

-

1

-

- 1,000 -

-

675

-

-

470

-

-

87

-

-

77

-

-

75

-

-

80

-

-

78

-

-

79

-

UNITS

Bits

LSB

LSB

LSB

µA

%

ppm

FSR/°C

µA/°C

mA

V

MSPS

ns

ns

pV • s

V/µs

ps

ps

dBc

dBc

dBc

dBc

dBc

dBc

3

FN4071.12

September 20, 2006

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