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HI5741-EVS(2000) Просмотр технического описания (PDF) - Intersil

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Компоненты Описание
производитель
HI5741-EVS
(Rev.:2000)
Intersil
Intersil Intersil
HI5741-EVS Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
HI5741
Absolute Maximum ratings TA = 25oC
Digital Supply Voltage VCC to DGND . . . . . . . . . . . . . . . . . . . +5.5V
Negative Digital Supply Voltage DVEE to DGND . . . . . . . . . . -5.5V
Negative Analog Supply Voltage AVEE to AGND, ARTN . . . . . -5.5V
Digital Input Voltages (D13-D0, CLK) to DGND. . . . . DVCC to -0.5V
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . ±2.5mA
Voltage from CTRL AMP IN to AVEE . . . . . . . . . . . . . . . . 2.5V to 0V
Control Amplifier Output Current . . . . . . . . . . . . . . . . . . . . . ±2.5mA
Reference Input Voltage Range . . . . . . . . . . . . . . . . . .-3.7V to AVEE
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature
HI5741BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications TAAVE=E2,5DoVCEE = -4.94 to -5.46V, VCC = +4.75 to +5.25V, VREF = Internal,
PARAMETER
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
(Notes 5)
Differential Linearity Error, DNL
Offset Error, IOS
Full Scale Gain Error, FSE
Offset Drift Coefficient
Full Scale Output Current, IFS
Output Voltage Compliance Range
DYNAMIC CHARACTERISTICS
Throughput Rate
Output Voltage Settling Time
(1/16th Scale Step Across Segment)
Singlet Glitch Area, GE (Peak)
Output Slew Rate
Output Rise Time
Output Fall Time
Spurious Free Dynamic Range within a Window
(Note 4)
Spurious Free Dynamic Range to Nyquist
(Notes 4)
TEST CONDITIONS
“Best Fit Straight Line”, TA = 25oC
“Best Fit Straight Line”, TA = -40oC to 85oC
(Note 5) TA = 25oC
(Note 5)
(Notes 3, 5)
(Note 4)
(Note 4)
(Note 4)
RL = 64(Note 4) - Settling to 0.024%
RL = 64(Note 4) - Settling to 0.012%
RL = 64(Note 4)
RL = 64Ω, DAC Operating in Latched Mode (Note 4)
RL = 64Ω, DAC Operating in Latched Mode (Note 4)
RL = 64Ω, DAC Operating in Latched Mode (Note 4)
fCLK = 10 MSPS, fOUT = 1.23MHz, 2MHz Span
fCLK = 20 MSPS, fOUT = 5.055MHz, 2MHz Span
fCLK = 40 MSPS, fOUT = 16MHz, 10MHz Span
fCLK = 50 MSPS, fOUT = 10.1MHz, 2MHz Span
fCLK = 80 MSPS, fOUT = 5.1MHz, 2MHz Span
fCLK = 100 MSPS, fOUT = 10.1MHz, 2MHz Span
fCLK = 10 MSPS, fOUT = 1.023MHz, 5MHz Span
fCLK = 10 MSPS, fOUT = 2.02MHz, 5MHz Span
fCLK = 25 MSPS, fOUT = 2.02MHz, 12.5MHz Span
fCLK = 50 MSPS, fOUT = 5.055MHz, 25MHz Span
fCLK = 75 MSPS, fOUT = 7.52MHz, 37.5MHz Span
fCLK = 100 MSPS, fOUT = 10.1MHz, 50MHz Span
HI5741BI
TA = -40oC TO 85oC
MIN TYP MAX
14
-
-
-
1.0 1.5
-
-
1.75
-
0.5 1.0
-
8
75
-
3.2
10
-
-
0.05
- -20.48 -
-1.25
-
0
100
-
-
-
11
-
-
20
-
-
1
-
- 1,000 -
-
675
-
-
470
-
-
87
-
-
77
-
-
75
-
-
80
-
-
78
-
-
79
-
-
86
-
-
85
-
-
77
-
-
74
-
-
73
-
-
71
-
UNITS
Bits
LSB
LSB
LSB
µA
%
µA/oC
mA
V
MSPS
ns
ns
pV • s
V/µs
ps
ps
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
3-3

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