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SSTL16877DGG

14-bit SSTL_2 registered driver with differential clock inputs

Philips Electronics 

Philips Semiconductors

14-bit SSTL_2 registered driver with

differential clock inputs

Product specification

SSTL16877

FEATURES

• Stub-series terminated logic for 2.5 V VDDQ (SSTL_2)

• Optimized for DDR (Double Data Rate) SDRAM applications

• Supports SSTL_2 signal inputs and outputs

• Flow-through architecture optimizes PCB layout

• Meets SSTL_2 class I and class II specifications

• Latch-up protection exceeds 500mA per JEDEC Std 17

• ESD protection exceeds 2000 V per MIL STD 833 Method 3015

and 200 V per Machine Model

• Full DDR solution provided when used with PCK877 and CBT3867

DESCRIPTION

The SSTL16877 is a 14-bit SSTL_2 registered driver with differential

clock inputs, designed to operate between 2.3 V and 2.7 V. VDDQ

must not exceed VCC. Inputs are SSTL_2 type with VREF normally at

0.5*VDDQ. The outputs support class I which can be used for

standard stub-series applications or capacitive loads. Master reset

(RESET) asynchronously resets all registers to zero.

The SSTL16877 is intended to be incorporated into standard DIMM

(Dual In-Line Memory Module) designs defined by JEDEC, such as

DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules.

Different from traditional SDRAM, DDR SDRAM transfers data on

both clock edges (rising and falling), thus doubling the peak bus

bandwidth. A DDR DRAM rated at 166 MHz will have a burst rate of

333 MHz. The modules require between 23 and 27 registered

control and address lines, so two 14-bit wide devices will be used on

each module. The SSTL16877 is intended to be used for SSTL_2

input and output signals.

The device data inputs consist of differential receivers. One

differential input is tied to the input pin while the other is tied to a

reference input pad, which is shared by all inputs.

The clock input is fully differential to be compatible with DRAM

devices that are installed on the DIMM. However, since the control

inputs to the SDRAM change at only half the data rate, the device

must only change state on the positive transition of the CLK signal.

In order to be able to provide defined outputs from the device even

before a stable clock has been supplied, the device must support an

asynchronous input pin (reset), which when held to the LOW state

will assume that all registers are reset to the LOW state and all

outputs drive a LOW signal as well.

PIN CONFIGURATION

Q1 1

Q2 2

GND 3

VDDQ 4

Q3 5

Q4 6

Q5 7

GND 8

VDDQ 9

Q6 10

Q7 11

VDDQ 12

GND 13

Q8 14

Q9 15

VDDQ 16

GND 17

Q10 18

Q11 19

Q12 20

VDDQ 21

GND 22

Q13 23

Q14 24

48 D1

47 D2

46 GND

45 VCC

44 D3

43 D4

42 D5

41 D6

40 D7

39 CLK–

38 CLK+

37 VCC

36 GND

35 VREF

34 RESET

33 D8

32 D9

31 D10

30 D11

29 D12

28 VCC

27 GND

26 D13

25 D14

SW00311

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25°C; tr =tf v2.5 ns

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

tPHL/tPLH

Propagation delay; CLK to Qn

CL = 30 pF; VDDQ = 2.5 V

2.4

CI

Input capacitance

VCC = 2.5 V

2.9

NOTES:

1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD VCC2 x fi )ȍ (CL VCC2 fo) where:

fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V;

ȍ (CL VCC2 fo) = sum of the outputs.

UNIT

ns

pF

ORDERING INFORMATION

PACKAGES

48-Pin Plastic TSSOP Type I

TEMPERATURE RANGE

0°C to +70°C

ORDER CODE

SSTL16877 DGG

DWG NUMBER

SOT362-1

2000 Apr 20

2

853-2198 23523

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