7872 Просмотр технического описания (PDF) - MAXWELL TECHNOLOGIES
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7872 Datasheet PDF : 11 Pages
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14-Bit A/D Converter
7872
PARAMETER
TABLE 10. 7872 DC ELECTRICAL CHARACTERISTICS FOR POWER REQUIREMENTS
(VDD = 5V ±5%, VSS = -5 V ± 5%, TA = -55 TO 125 °C UNLESS OTHERWISE SPECIFIED)
SYMBOL CONDITIONS
REQUIREMENTS
Positive Supply Voltage
Negative Supply Voltage
Positive Supply Current
Negative Supply Current
Power Dissipation
VDD 5% for Specified Performance
5
VSS 5% for Specified Performance
-5
IDD
Typically 6mA
13
ISS
Typically 4mA
6
PD
Typically 50mW
95
UNITS
V
V
mA max
mA max
mW max
PARAMETER/CONDITION
TABLE 11. 7872 TIMING CHARACTERISTICS 1,2
(VDD = 5V ±5%, VSS = -5 V ± 5%, TA = -55 TO 125 °C UNLESS OTHERWISE SPECIFIED)
SYMBOL
SUBGROUPS
MIN
MAX
UNITS
CONVST Pulse Width
SSTRB to SCLK Falling Edge Setup Time
SCLK Cycle Time 3
SCLK to Valid Data Delay: CL = 35 pF 4
SCLD Rising Edge to SSTRB
Bus Relinquish Time After SCLK
t1
9, 10, 11 50
--
ns
t10
9, 10, 11 100
--
ns
t11
9, 10, 11 440
--
ns
t12
9, 10, 11
--
155
ns
t13
9, 10, 11
20
150
ns
t14
9, 10, 11
4
100
ns
1. All input signals are specified with tr = tr = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2. Serial timing is measured with a 4.7 kΩ pull-up resistor on SDATA and SSTRB and a 2 kΩ pull-up resistor on SCLK. The
capacitance on all three outputs is 35 pF.
3. SCLK mark/space ration (measured from a voltage level of 1.6 V) is 40/60 to 60/40.
4. SDATA will drive higher capacitive loads, but this will add to t12 since it increases the external RC time constant (4.7kΩ/CL) and
hence, the time to reach 2.4 V.
5.21.02 Rev 4
All data sheets are subject to change without notice 5
©2001 Maxwell Technologies
All rights reserved.
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