MT8976AE Просмотр технического описания (PDF) - Mitel Networks
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MT8976AE Datasheet PDF : 26 Pages
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MT8976 ISO-CMOS
TxA 1
TxB 2
DSTo 3
NC 4
RxA 5
RxB 6
RxD 7
CSTi1 8
TxFDL 9
TxFDLClk 10
NC 11
CSTi0 12
E8Ko 13
VSS 14
28 VDD
27 IC
26 F0i
25 E1.5i
24 C1.5i
23 RxSF
22 TxSF
21 C2i
20 RxFDL
19 DSTi
18 RxFDLClk
17 CSTo
16 XSt
15 XCtl
NC
NC
RxA
RxB
RxD
NC
CSTi1
TxFDL
NC
TxFDLClk
NC
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
C1.5i
RxSF
TxSF
NC
NC
C2i
NC
NC
NC
NC
RxFDL
28 PIN CERDIP/PDIP
44 PIN PLCC
Figure 2 - Pin Connections
.
Pin Description
Pin #
DIP PLCC
Name
Description
12
TxA
Transmit A Output. Unipolar output that can be used in conjunction with TxB and
external line driver circuitry to generate the bipolar DS1 signal.
23
TxB
Transmit B Output. Unipolar output that can be used in conjunction with TxA and
external line driver circuitry to generate the bipolar DS1 signal.
35
DSTo
Data ST-BUS Output. A 2048 kbit/s serial output stream which contains the 24
PCM or data channels received from the DS1 line.
44
NC
No Connection.
59
RxA
Receive A Complementary Input. Accepts a unipolar split phase signal decoded
externally from the received DS1 bipolar signal. This input, in conjunction with RxB,
detects bipolar violations in the received signal.
6 10
RxB
Receive B Complementary Input. Accepts a unipolar split phase signal decoded
externally from the received DS1 bipolar signal. This input, in conjunction with RxA,
detects bipolar violations in the received signal.
7 11
RxD Receive Data Input. Unipolar RZ data signal decoded from the received DS1
signal. Generally the signals input at RxA and RxB are combined externally with a
NAND gate and the resulting composite signal is input at this pin.
8 13
CSTi1
Control ST-BUS Input #1. A 2048 kbit/s serial control stream which carries 24 per-
channel control words.
9 14
TxFDL
Transmit Facility Data Link (Input). A 4 kHz serial input stream that is multiplexed
into the FDL position in the ESF mode, or the Fs pattern when in SLC-96 mode. It is
clocked in on the rising edge of TxFDLClk.
10 16 TxFDLClk Transmit Facility Data Link Clock (Output). A 4 kHz clock used to clock in the FDL
data.
11
NC
No connection.
4-30
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