NE56611-25 Просмотр технического описания (PDF) - Philips Electronics

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NE56611-25

System reset

Philips Electronics 

Philips Semiconductors

System reset

Product data

NE56610/11/12-XX

TECHNICAL DESCRIPTION

The NE56610/11/12-XX devices comprise a family of devices

designed to monitor the supply voltage and output a RESET signal

whenever the supply voltage sags below an acceptable system level

or when supply voltage interruptions occur. Each of the three

devices of the family are available with a fixed detection threshold

voltage (2.5, 2.7, 2.9, 3.9, 4.2, 4.5 V). The device family is very

versatile and adaptable for a wide variety of applications.

The devices are designed to have a detection threshold hysteresis

of 50 mV typical. When the supply voltage delivered to the device

falls to the detection sense level (VS), a RESET is output and not

released until the supply voltage rises to the level of VS or greater.

These levels are termed VL (synonymous with VS) and VH, and the

difference of VH – VL = VHYS (the hysteresis voltage value).

Internally, the devices incorporate a fixed internal digital timer which,

when activated, produces a fixed internal delay before a RESET

signal is output. This delay can not be influenced externally. The

NE56510 has an internal delay of 50 ms, while the NE56611 and

NE56612 have internal delays of 100 ms and 200 ms respectively.

Incorporating a delay in the output RESET prevents output

oscillations from occurring and helps ensure system supply voltages

are adequate and stabilized before the microprocessor is placed into

full operation. Where there is little or no delay in output RESET,

there is a possibility of output oscillations occurring, particularly

where high impedance supply sources are used.

In addition, the devices have a manual reset (M/R) pin, which when

pulled to a HIGH voltage state, forces a RESET signal at the output.

The M/R pin should always be connected to ground when manual

reset is not used.

The output of the NE56610/11/12 utilizes a low side open collector

topology, requiring the user to use an external pull-up resistor (RPU)

to the VCC power source. Although this may be regarded as a

disadvantage, it is an advantage in many sensitive applications. The

open drain output topology does not have the capability of sourcing

reset current to a microprocessor when both are operated from a

common supply. It is for this reason the device family offers a safe

inter-connect to a wide variety of microprocessors.

VCC 5

R

OSC

DELAY

TQ

R

4 VOUT RESET

M/R 1

R

R

R

R

NE56610/11/12-XX

Figure 16. Functional diagram

R

3 GND

R

2 SUB

SL01382

2003 Oct 31

8

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