NE56611(2001) Просмотр технического описания (PDF) - Philips Electronics
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NE56611 Datasheet PDF : 9 Pages
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Philips Semiconductors
NE56610/11/12 Series
System Reset
TIMING DIAGRAM
The Timing Diagram shown in Figure 15 depicts the operation
of the device. Letters indicate events on the Time axis.
A: At start-up, event "A", the VCC and Reset voltages begin to
rise. Also the Reset voltage initially rises but then abruptly
returns to a low state. This is due to VCC reaching the level
(approximately 0.8V) that activates the internal bias circuitry.
B: At event "B", the "H" transport delay time (TPLH) is initiated.
This is caused by and coincident to VCC reaching the threshold
level of VSH. At this level the device is in full operation. The
Reset output remains off as VCC rises above VSH. This is
normal.
C: At event "C" VCC is above the undervoltage detect
threshold and the "H" transport delay time (TPLH) has elapsed.
At this point the device removes the hold on the VOUT reset.
VOUT Reset goes high.
In a microprocessor based system these events remove the
reset from the microprocessor, allowing it to function normally.
D-E: At "D", VCC begins to ramp down causing VOUT to follow
it. VCC continues to sag until the VSL undervoltage threshold is
reached at "E". At that time, reset signal is generated (VOUT
Reset goes low).
E-F: Between "E" and "F", VCC recovers and starts
increasing.
F: At "F", VCC reaches the VSH upper threshold. Once again,
the "H" transport delay time (TPLH) is initiated.
G: At "G", VCC is above the undervoltage detect threshold
and the "H" transport delay time (TPLH) has elapsed. At this point
the device removes the hold on the VOUT reset. VOUT Reset
goes high.
H-J: At event "H", VCC is normal, but a manual reset signal
from the logic device is applied at the M/R pin. With the falling
edge of the manual reset signal, the "H" transport delay time
(TPLH) is initiated. At "J", transport delay time (TPLH) has
elapsed and the Vout reset goes high.
K: At event "K" VCC sags to the point where the VSL
undervoltage threshold point is reached and at that level VOUT
reset goes low.
L: At event "L" the VCC voltage has deteriorated to a level
where normal internal circuit bias is no longer able to maintain a
VOUT reset and as a result may exhibit a slight rise to something
less than 0.8V. As VCC decays even further, VOUT reset also
decreases to zero.
Figure 15. Timing Diagram
V
B
VSH
VSL
VCC
C
DF
H
VS
K L ∆VS
V
VOUT
AB
V
M/R
TPLH
CE
VRES
TPLH
G
H
TPLH
J
KL
TIME
February 23, 2001
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