82378ZB Просмотр технического описания (PDF) - Intel

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82378ZB

82378ZB SYSTEM I/O (SIO) AND 82379AB SYSTEM I/O APIC (SIO.A)

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82378ZB (SIO) AND 82379 (SIO.A)

1.0. ARCHITECTURAL OVERVIEW

The major functions of the SIO and SIO.A components are broken up into blocks as shown in the SIO and SIO.A

Component Block Diagrams. A description of each block is provided below.

PCI Bus Interface

The PCI Bus Interface provides the interface between the SIO/SIO.A and the PCI Bus. The SIO/SIO.A provides

both a master and slave interface to the PCI Bus. As a PCI master, the SIO/SIO.A runs cycles on behalf of

DMA, ISA masters, and the internal data buffer management logic when buffer flushing is required. The

SIO/SIO.A burstS a maximum of two Dwords when reading from PCI memory, and one Dword when writing to

PCI memory. The SIO/SIO.A does not generate PCI I/O cycles as a master. As a PCI slave, the SIO/SIO.A

accepts cycles initiated by PCI masters targeted for the SIO/SIO.A internal register set or the ISA Bus. The

SIO/SIO.A accepts a maximum of one data transaction before terminating the transaction. This supports the

Incremental Latency Mechanism as defined in the Peripheral Component Interconnect (PCI) Specification.

As a master, the SIO/SIO.A generates address and command signal (C/BE#) parity for read and write cycles,

and data parity for write cycles. As a slave, the SIO/SIO.A generates data parity for read cycles. Parity checking

is not supported. The SIO/SIO.A also provides support for system error reporting by generating a Non-

Maskable-Interrupt (NMI) when SERR# is driven active.

The SIO/SIO.A, as a resource, can be locked by any PCI master. In the context of locked cycles, the entire

SIO/SIO.A subsystem (including the ISA Bus) is considered a single resource.

The SIO/SIO.A directly supports the PCI Interface running at either 25 MHz or 33 MHz. If a frequency of less

than 33 MHz is required (not including 25 MHz), a SYSCLK divisor value (as indicated in the ISA Clock Divisor

Register) must be selected that guarantees that the ISA Bus frequency does not violate the 6 MHz to 8.33 MHz

SYSCLK range.

PCI Arbiter

The PCI arbiter provides support for six PCI masters; the Host Bridge, SIO/SIO.A, and four PCI masters. The

arbiter can be programmed for a purely rotating scheme, fixed, or a combination of the two. The Arbiter can also

be programmed to support bus parking. This gives the Host Bridge default access to the PCI Bus when no other

device is requesting service. The arbiter can be disabled if an external arbiter is used.

Data Buffers

To isolate the slower ISA Bus from the PCI Bus, the SIO/SIO.A provides two types of data buffers. One Dword-

deep posted write buffer is provided for the posting of PCI initiated memory write cycles to the ISA Bus. The

second buffer is a bi-directional, 8-byte line buffer used for ISA master and DMA accesses to the PCI Bus. All

DMA and ISA master read and write cycles go through the 8-byte line buffer. The data buffers also provide the

data assembly or disassembly when needed for transactions between the PCI and ISA Buses. Buffering is

programmable and can be enabled or disabled through software.

ISA Bus Interface

The SIO/SIO.A incorporates a fully ISA-Bus compatible master and slave interface. The SIO/SIO.A directly

drives six ISA slots without external data or address buffering. The ISA interface also provides byte swap logic,

I/O recovery support, wait-state generation, and SYSCLK generation. The SIO/SIO.A supports ISA Bus

frequencies from 6 to 8.33 MHz.

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