82378ZB Просмотр технического описания (PDF) - Intel
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82378ZB Datasheet PDF : 137 Pages
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82378ZB (SIO) AND 82379AB (SIO.A)
E
As an ISA master, the SIO/SIO.A generates cycles on behalf of DMA, Refresh, and PCI master initiated cycles.
The SIO/SIO.A supports compressed cycles when accessing ISA slaves (i.e., ZEROWS# asserted). As an ISA
slave, the SIO/SIO.A accepts ISA master accesses targeted for the SIO/SIO.A internal register set or ISA
master memory cycles targeted for the PCI Bus. The SIO/SIO.A does not support ISA master initiated I/O cycles
targeted for the PCI Bus.
The SIO/SIO.A also monitors ISA master to ISA slave cycles to generate SMEMR# or SMEMW#, and to support
data byte swapping, if necessary.
DMA
The DMA controller in the SIO/SIO.A incorporates the functionality of two 82C37 DMA controllers with seven
independently programmable channels. Each channel can be programmed for 8- or 16-bit DMA device size. The
DMA controller is also responsible for generating ISA refresh cycles.
For the 82378ZB, ISA-compatible or fast DMA type "A", type "B", or type "F" timings are supported and 32-bit
addressing is supported as an extension of the ISA-compatible specification. The SIO supports an enhanced
feature called Scatter/Gather (S/G). This feature provides the capability of transferring multiple buffers between
memory and I/O without CPU intervention. In S/G mode, the DMA can read the memory address and word count
from an array of buffer descriptors, located in system memory, called the S/G Descriptor (SGD) Table. This
allows the DMA controller to sustain DMA transfers until all of the buffers in the SGD table are read.
For the SIO.A, the DMA supports 8-/16-bit device size using ISA-compatible timings and 27-bit addressing as an
extension of the ISA-compatible specification. Scatter/Gather is not supported.
Timer Block
The timer block contains three counters that are equivalent in function to those found in one 82C54
programmable interval timer. These three counters are combined to provide the System Timer function, Refresh
Request, and speaker tone. The three counters use the 14.31818 MHz OSC input for a clock source.
In addition to the three counters, the SIO/SIO.A provides a programmable 16-bit BIOS timer. This timer can be
used by BIOS software to implement timing loops. The timer uses the ISA system clock (SYSCLK) divided by 8
as a clock source. An 8:1 ratio between the SYSCLK and the BIOS timer clock is always maintained. The
accuracy of the BIOS timer is ± 1 ms.
Utility Bus (X-Bus) Logic
The SIO/SIO.A provides four encoded chip selects that are decoded externally to provide chip selects for flash
BIOS, real time clock, keyboard/Mouse Controller, floppy controller, two serial ports, one parallel port, and an
IDE hard disk drive. The SIO/SIO.A provides the control for the buffer that isolates the lower 8 bits of the Utility
Bus from the lower 8 bits of the ISA Bus. In addition to providing the encoded chip selects and Utility Bus buffer
control, the SIO/SIO.A also provides Port 92 functions (Alternate Reset and Alternate A20), Coprocessor error
reporting, the Floppy DSKCHG function, and a mouse interrupt input.
Interrupt Controller Block
The SIO/SIO.A provides an ISA compatible interrupt controller that incorporates the functionality of two 82C59
interrupt controllers. The two interrupt controllers are cascaded so that 14 external and two internal interrupts are
possible.
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