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HI-8683

ARINC INTERFACE DEVICE ARINC 429 & 561 Serial Data to 8-Bit Parallel Data

Holt Integrated Circuits 

HI-8683, HI-8684

PIN DESCRIPTIONS

SIGNAL

FUNCTION

DESCRIPTION

DATA RDY OUTPUT

D1 to D7

GND

READ

PARITY ENB

OUTPUT

POWER

INPUT

INPUT

ERROR

OUTPUT

INA

INB

RINA/RINA-10

RINB/RINB-10

RESET

TESTA

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

TESTB

INPUT

GAPCLK

INPUT

Vcc

POWER

Receiver data ready flag. A high level indicates data is available in the receive

buffer. Flag goes low when the first 8-bit byte is read.

8-bit parallel data bus (tri-state)

0V

Read strobe. A low level transfers receive buffer data to the data bus

Parity Enable - A high level activates odd parity checking which replaces the

32nd ARINC bit with an error bit. Otherwise, the 32nd ARINC bit is unchanged

Error Flag. A high level indicates a bit count error (number of ARINC bits was

less than or greater than 32) and/or a parity error if parity detection was enabled

(PARITY ENB high)

Positive digital serial data input (HI-8683 only)

Negative digital serial data input (HI-8683 only)

Positive direct ARINC serial data input (HI-8684 & HI-8684-10 only)

Negative direct ARINC serial data input (HI-8684 & HI-8684-10 only)

Internal logic states are initialized with a low level

Used in conjunction with the TESTB input to bypass the built-in analog line

receiver circuitry (HI-8684 & HI-8684-10 only)

Used in conjunction with the TESTA input to bypass the built-in analog line

receiver circuitry (HI-8684 & HI-8684-10 only)

Gap Clock. Determines the minimum time required between ARINC words for

detection. The minimum word gap time is between 16 and 17 clock cycles of

this signal.

+5V ±10% supply

FUNCTIONAL DESCRIPTION

The HI-8683 and HI-8684 are serial to 8-bit parallel convert-

ers. The incoming data stream is serially shifted into an input

register, checked for errors, and then transferred in parallel to

a 32-bit receive buffer. The receive data can be accessed us-

ing four 8-bit parallel read operations while the next serial

data steam is being received.

RECEIVER INPUTS

Figure 1 is a block diagram of both the HI-8683 and HI-8684.

The difference between the two products is the HI-8684 has

a built-in line receiver whereas the HI-8683 is strictly a digital

device and requires an external ARINC line receiver such as

the Holt HI-8482, HI-8588 or HI-8590 to interface to the

ARINC 429 bus.

HI-8684 Line Receiver

Typically 35KΩ resistors are in series with both the RINA and

RINB ARINC 429 inputs. They connect to level translators

whose resistance to GND is typically 10KΩ. After level trans-

lation, the buffered inputs drive a differential amplifier. The

differential signal is compared to levels derived from a divider

between VCC and GND. The nominal settings correspond to

a One/Zero amplitude of 6.0V and a Null amplitude of 3.3V. A

valid ARINC One/Zero input sets a latch and a Null input re-

sets the latch.

Since any added external series resistance will affect the volt-

age translation, the HI-8684-10 is available with 25KΩ of the

35KΩ series resistance required for proper ARINC 429 level

detection. The remaining 10KΩ required that must be added

can be incorporated in other external circuitry such as light-

ning protection. Except for the different input series resis-

tance, the HI-8684 and HI-8684-10 are identical.

HOLT INTEGRATED CIRCUITS

2

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