MC74AC160 Просмотр технического описания (PDF) - Motorola => Freescale
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MC74AC160 Datasheet PDF : 14 Pages
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MC74AC160 MC74ACT160 MC74AC162 MC74ACT162
FUNCTIONAL DESCRIPTION
The MC74AC160/74ACT160 and MC74AC162/74ACT162
count modulo-10 in the BCD (8421) sequence. From state 9
(HLLH) they increment to state 0 (LLLL). The clock inputs of
all flip-flops are driven in parallel through a clock buffer. Thus
all changes of the Q outputs (except due to Master Reset of the
′160) occur as a result of, and synchronous with, the
LOW-to-HIGH transition of the CP input signal. The circuits
have four fundamental modes of operation, in order of
precedence: asynchronous reset (′160), synchronous reset
(′162), parallel load, count-up and hold. Five control inputs —
Master Reset (MR, ′160), Synchronous Reset (SR,′162),
Parallel Enable (PE), Count Enable Parallel (CEP) and Count
Enable Trickle (CET) — determine the mode of operation, as
shown in the Mode Select Table. A LOW signal on MR
overrides all other inputs and asynchronously forces all
outputs LOW. A LOW signal on SR overrides counting and
parallel loading and allows all outputs to go LOW on the next
rising edge of CP. A LOW signal on PE overrides counting and
allows information on the Parallel Data (Pn) inputs to be loaded
into the flip-flops on the next rising edge of CP. With PE and MR
(′160) or SR (′162) HIGH, CEP and CET permit counting when
both are HIGH. Conversely, a LOW signal on either CEP or
CET inhibits counting.
The MC74AC160/74ACT160 and MC74AC162/74ACT162
use D-type edge-triggered flip-flops and changing the SR, PE,
CEP and CET inputs when the CP is in either state does not
cause errors, provided that the recommended setup and hold
times, with respect to the rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is HIGH
and counter is in state 9. To implement synchronous
multistage counters, the TC outputs can be used with the CEP
and CET inputs in two different ways. Please refer to the
MC74AC568 data sheet. The TC output is subject to decoding
spikes due to internal race conditions and is therefore not
recommended for use as a clock or asynchronous reset for
flip-flops, counters or registers. In the MC74AC160/74ACT160
and MC74AC162/74ACT162 decade counters, the TC output is
fully decoded and can only be HIGH in state 9. If a decade
counter is preset to an illegal state, or assumes an illegal state
when power is applied, it will return to the normal sequence
within two counts, as shown in the State Diagram.
Logic Equations: Count Enable = CEP• CET• PE
TC = Q0• Q1• Q2• Q3• CET
MODE SELECT TABLE
*SR PE CET
L
X
X
H
L
X
H
H
H
H
H
L
H
H
X
*For ′162 only
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
CEP
X
X
H
X
L
Action on the Rising
Clock Edge ( )
Reset (Clear)
Load (Pn → Qn)
Count (Increment)
No Change (Hold)
No Change (Hold)
STATE DIAGRAM
0
1
2
3
4
15
5
14
6
13
7
12 11 10
9
8
FACT DATA
5-2
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