MSM54V24632A Просмотр технического описания (PDF) - Oki Electric Industry

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MSM54V24632A

131,072-Word x 32-Bit x 2-Bank SGRAM without Graphics Functions

Oki Electric Industry 

¡ Semiconductor

MSM54V24632A

PIN DESCRIPTION

CLK

CS

CKE

Address

A9

RAS

CAS

WE

DQM0

~DQM3

DQi

Fetches all inputs at the "H" edge.

Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,

DQM0, DQM1, DQM2 and DQM3.

Masks system clock to deactivate the subsequent CLK operation.

If CKE is deactivated, system clock will be masked that the subsequent CLK operation is deactivated.

CKE should be asserted at least one cycle prior to a new command.

Row & column multiplexed.

Row address: RA0 – RA8

Column address: CA0 – CA7

Selects bank to be activated during row address latch time and selects bank for precharge and read/

write during column address latch time. A9= "L" : Bank A, A9= "H" : Bank B

Functionality depends on the combination. For details, see the function truth table.

Masks the read data of two clocks later when DQM0~DQM3 is set "H" at the "H" edge of the clock signal.

Masks the write data of the same clock when DQM0~DQM3 is set "H" at the "H" edge of the clock signal.

Data inputs/outputs are multiplexed on the same pin.

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