W83977ATF Просмотр технического описания (PDF) - Winbond
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W83977ATF Datasheet PDF : 212 Pages
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W83977ATF
7.1 BASIC I/O FUNCTIONS ...................................................................................................................................108
7.2 ALTERNATE I/O FUNCTIONS ......................................................................................................................... 110
7.2.1 Interrupt Steering ..................................................................................................................................110
7.2.2 Watch Dog Timer Output ......................................................................................................................111
7.2.3 Power LED ............................................................................................................................................ 111
7.2.4 General Purpose Address Decoder ....................................................................................................... 111
7.2.5 General Purpose Write Strobe .............................................................................................................. 111
8.0 PLUG AND PLAY CONFIGURATION..................................................................................................112
8.1 COMPATIBLE PNP..........................................................................................................................................112
8.1.1 Extended Function Registers .................................................................................................................112
8.1.2 Extended Functions Enable Registers (EFERs) .................................................................................... 113
8.1.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs) .................. 113
8.2 CONFIGURATION SEQUENCE.......................................................................................................................... 113
9.0 ACPI REGISTERS FEATURES .............................................................................................................. 115
9.1 SMI TO SCI/SCI TO SMI AND BUS MASTER................................................................................................. 116
9.2 POWER MANAGEMENT TIMER .......................................................................................................................117
9.3 ACPI REGISTERS (ACPIRS).......................................................................................................................... 118
9.3.1 Power Management 1 Status Register 1 (PM1STS1) ............................................................................ 118
9.3.2 Power Management 1 Status Register 2 (PM1STS2) ............................................................................ 119
9.3.3 Power Management 1 Enable Register 1(PM1EN1)............................................................................. 120
9.3.4 Power Management 1 Enable Register 2 (PM1EN2)............................................................................ 120
9.3.5 Power Management 1 Control Register 1 (PM1CTL1).........................................................................121
9.3.6 Power Management 1 Control Register 2 (PM1CTL2).........................................................................121
9.3.7 Power Management 1 Control Register 3 (PM1CTL3).........................................................................122
9.3.8 Power Management 1 Control Register 4 (PM1CTL4).........................................................................122
9.3.9 Power Management 1 Timer 1 (PM1TMR1) ......................................................................................... 123
9.3.10 Power Management 1 Timer 2 (PM1TMR2) .......................................................................................123
9.3.11 Power Management 1 Timer 3 (PM1TMR3) .......................................................................................124
9.3.12 Power Management 1 Timer 4 (PM1TMR4) .......................................................................................125
9.3.13 General Purpose Event 0 Status Register 1 (GP0STS1)...................................................................... 125
9.3.14 General Purpose Event 0 Status Register 2 (GP0STS2)...................................................................... 126
9.3.15 General Purpose Event 0 Enable Register 1 (GP0EN1) .....................................................................127
9.3.16 General Purpose Event 0 Enable Register 2 (GP0EN2) .....................................................................128
9.3.17 General Purpose Event 1 Status Register 1 (GP1STS1)...................................................................... 128
9.3.18 General Purpose Event 1 Status Register 2 (GP1STS2)...................................................................... 129
9.3.19 General Purpose Event 1 Enable Register 1 (GP1EN1) .....................................................................129
9.3.20 General Purpose Event 1 Enable Register 2 (GP1EN2) .....................................................................130
9.3.21 Bit Map Configuration Registers.........................................................................................................131
10.0 SERIAL IRQ............................................................................................................................................. 132
10.1 START FRAME ............................................................................................................................................. 133
10.2 IRQ/DATA FRAME....................................................................................................................................... 133
10.3 STOP FRAME................................................................................................................................................134
10.4 RESET AND INITIALIZATION......................................................................................................................... 134
11.0 CONFIGURATION REGISTER............................................................................................................ 135
11.1 CHIP (GLOBAL) CONTROL REGISTER ..........................................................................................................135
11.2 LOGICAL DEVICE 0 (FDC) .......................................................................................................................... 141
11.3 LOGICAL DEVICE 1 (PARALLEL PORT) ........................................................................................................ 146
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Publication Release Date: Apr 2001
Revision 0.53
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