STPCC03 Просмотр технического описания (PDF) - STMicroelectronics

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STPCC03

PC Compatible Embeded Microprocessor

STMicroelectronics 

GENERAL DESCRIPTION

The Video output pipeline of the STPC Consumer-

S interfaces directly to the internal digital TV en-

coder. It takes a 24 bit RGB non-interlaced pixel

stream and converts to a multiplexed 4:2:2 YCrCb

8 bit output stream, the logic includes a progres-

sive to interlaced scan converter and logic to in-

sert appropriate CCIR656 timing reference codes

into the output stream. It facilitates the high quality

display of VGA or full screen video streams re-

ceived via the Video input port to standard NTSC

or PAL televisions.

The digital PAL/NTSC encoder outputs interlaced

or non-interlaced video in PAL-B,D,G,H,I PAL-N,

PAL-M or NTSC-M standards and “NTSC- 4.43” is

also possible.

The four frame (for PAL) or 2 frame (for NTSC)

burst sequences are internally generated, subcar-

rier generation being performed numerically with

CKREF as reference. Rise and fall times of syn-

chronisation tips and burst envelope are internally

controlled according to the relevant ITU-R and

SMPTE recommendations.

Video output signals are directed to four analog

output pins through internal D/A converters giving,

simultaneous R,G,B and composite CVBS out-

puts.

IDE INTERFACE

An industry standard EIDE (ATA 2) controller is

built into the STPC Consumer-S. The IDE port is

capable of supporting a total of four devices.

POWER MANAGEMENT

The STPC Consumer-S core is compliant with the

Advanced Power Management (APM) specifica-

tion to provide a standard method by which the

BIOS can control the power used by personal

computers. The Power Management Unit module

(PMU) controls the power consumption providing

a comprehensive set of features that control the

power usage and supports compliance with the

United States Environmental Protection Agency’s

Energy Star Computer Program. The PMU pro-

vides following hardware structures to assist the

software in managing the power consumption by

the system.

- System Activity Detection.

- Three power down timers.

- Doze timer for detecting lack of system activity

for short durations.

- Stand-by timer for detecting lack of system activ-

ity for medium durations

- Suspend timer for detecting lack of system activ-

ity for long durations.

- House-keeping activity detection.

- House-keeping timer to cope with short bursts of

house-keeping activity while dozing or in stand-by

state.

- Peripheral activity detection.

- Peripheral timer for detecting lack of peripheral

activity

- SUSP# modulation to adjust the system perform-

ance in various power down states of the system

including full power on state.

- Power control outputs to disable power from dif-

ferent planes of the board.

Lack of system activity for progressively longer

period of times is detected by the three power

down timers. These timers can generate SMI in-

terrupts to CPU so that the SMM software can put

the system in decreasing states of power con-

sumption. Alternatively, system activity in a power

down state can generate SMI interrupt to allow the

software to bring the system back up to full power

on state. The chip-set supports up to three power

down states: Doze state, Stand-by state and Sus-

pend mode. These correspond to decreasing lev-

els of power savings.

POWER DOWN

Power down puts the STPC Consumer-S into sus-

pend mode. The processor completes execution

of the current instruction, any pending decoded in-

structions and associated bus cycles. During the

suspend mode, internal clocks are stopped. Re-

moving power down, the processor resumes in-

struction fetching and begins execution in the in-

struction stream at the point it had stopped. Be-

cause of the static nature of the core, no internal

data is lost.

5/51

Release B

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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