TDA1541A Просмотр технического описания (PDF) - Philips Electronics
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TDA1541A Datasheet PDF : 12 Pages
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Philips Semiconductors
Stereo high performance 16-bit DAC
Product specification
TDA1541A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
THD
THD
tcs
α
|dIO|
|td|
SSVR
SSVR
SSVR
S/N
S/N
total harmonic distortion
including noise
−
at 0 dB;
note 3, Fig. 3, 4
−
total harmonic distortion
including noise
−
at −60 dB;
note 3, Fig. 3, 4
−
settling time ±1 LSB
−
channel separation
90
unbalance between outputs
note 4
−
time delay between outputs
−
supply voltage ripple rejection
VDD = +5 V;
note 4
−
supply voltage ripple rejection
VDD1 = −5 V;
note 4
−
supply voltage ripple rejection
VDD2 = −15 V;
note 4
−
signal-to-noise ratio
at bipolar zero
−
signal-to-noise ratio
at full scale
98
−95
0.0018
−42
0.79
0.5
98
< 0.1
−
−76
−84
−58
110
104
−90
0.0032
−
−
−
−
0.3
0.2
−
−
−
−
−
Timing (Fig. 5 and 6)
tr
tf
tCY
tHB
tLB
tFBRL
tRBFL
tSU;DAT
tHD;DAT
tHD;WS
tSU;WS
rise time
fall time
bit clock cycle time
bit clock HIGH time
bit clock LOW time
bit clock fall time to latch enable
rise time
bit clock rise time to latch enable
fall time
data set-up time
data hold time to bit clock
word select hold time
word select set-up time
−
−
32
−
−
32
156
−
−
46
−
−
46
−
−
0
−
−
0
−
−
32
−
−
0
−
−
0
−
−
32
−
−
Notes to the characteristics
1. To ensure no performance losses, permitted output voltage compliance is ±25 mV maximum.
2. Selections have been made with respect to the maximum differential linearity error (EdL):
TDA1541A/N2
bit 1-16 EdL < 1 LSB
TDA1541A/N2/R1
bit 1-16 EdL < 2 LSB
TDA1541A/N2/S1
bit 1-7 EdL < 0.5 LSB
bit 8-15 EdL < 1 LSB
bit 16 EdL < 0.75 LSB
UNIT
dB
%
dB
%
µs
dB
dB
µs
dB
dB
dB
dB
dB
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
February 1991
7
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