LRI512 Просмотр технического описания (PDF) - STMicroelectronics

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LRI512

Memory TAG IC 512 bit High Endurance EEPROM 13.56MHz, ISO 15693 Standard Compliant with E.A.S.

STMicroelectronics 

LRI512

VCD to LRI512 Frames

Frames are delimited by a Start of Frame (SOF)

and an End of Frame (EOF) and are implemented

using code violation. Unused options are reserved

for future use.

The LRI512 is ready to receive a new command

frame from the VCD after a delay of t2 after having

sent a response frame to the VCD (as specified in

Table 59).

The LRI512 generates a Power-on delay of tMINCD

after being activated by the powering field (as

specified in Table 59). After this delay, the LRI512

is ready to receive command frames from the

VCD.

Start of Frame (SOF)

The SOF defines the data coding mode the VCD

is to use for the following command frame.

The SOF sequence described in Figure 9 selects

the 1 out of 256 data coding mode.

The SOF sequence described in Figure 10 selects

the 1 out of 4 data coding mode.

The EOF sequence for either coding mode is de-

scribed in Figure 11.

Figure 9. SOF to Select 1 Out of 256 Data Coding Mode

9.44 µs

37.76 µs

Figure 10. SOF to Select 1 Out of 4 Data Coding Mode

37.76 µs

9.44 µs

AI06661

9.44 µs

37.76 µs

9.44 µs 9.44 µs

37.76 µs

Figure 11. EOF for Either Data Coding Mode

AI06660

9.44 µs 9.44 µs

37.76 µs

AI06662

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