LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
F-CE
F-OE
F-WE
F-RP
F-WP
F-A17, F-A18
S-A1 to S-A17,
F-A0 to F-A16
S-A0
S-CE
S-OE
S-WE
F-VCC
F-VPP
524,288 x 16 BIT
FLASH MEMORY
262,144 x 8 BIT
SRAM
I/O8 to
I/O15
I/O0 to
I/O7
GND
S-VCC
LRS1338A-2
Figure 2. LRS1338A Block Diagram
Table 1. Pin Descriptions
PIN
S-A1 to S-A17
F-A0 to F-A16
S-A0
F-A17 to F-A18
F-CE
S-CE
F-WE
S-WE
F-OE
S-OE
I/O0 to I/07
I/O8 to I/O15
F-RP
F-WP
F-VCC
F-VPP
S-VCC
GND
DESCRIPTION
Common Address Input Pins
Address Input Pin for SRAM
Address Input Pin for Flash Memory
Chip Enable Input Pin for Flash Memory
Chip Enable Input Pin for SRAM
Write Enable Input Pin for Flash Memory
Write Enable Input Pin for SRAM
Output Enable Input Pin for Flash Memory
Output Enable Input Pin for SRAM
Common Data Input/Output Pins
Data Input/Output Pins for Flash Memory
Reset/Deep Power Down Input Pin for Flash Memory
Write Protect Pin for Flash Memory’s Boot Block
Power Supply Pin for Flash Memory
Power Supply Pin for Flash Memory Write/Erase
Power Supply Pin for SRAM
Common Ground
2
Data Sheet