LRS1338A Просмотр технического описания (PDF) - Sharp Electronics

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LRS1338A

Stacked Chip 8M Flash Memory and 2M SRAM

Sharp Electronics 

LRS1338A

Stacked Chip (8M Flash & 2M SRAM)

Bus Operation

The local CPU reads and writes flash memory in-

system. All bus cycles to or from the flash memory con-

form to standard microprocessor bus cycles.

READ

Information can be read from any block, identifier

codes or status register independent of the VPP volt-

age. RP can be either VIH or VHH.

The first task is to write the appropriate read mode

command (Read Array, Read Identifier Codes, or Read

Status Register) to the CUI. Upon initial device power-

up or after exit from deep power-down mode, the device

automatically resets to read array mode. Five control

pins dictate the data flow in and out of the component:

CE, OE, WE, RP and WP. CE and OE must be driven

active to obtain data at the outputs. CE is the device

selection control, and when active enables the selected

memory device. OE is the data output (I/O0 - I/O15) con-

trol and when active drives the selected memory data

onto the I/O bus. WE must be at VIH and RP must be at

VIH or VHH. Figure 12 illustrates a read cycle.

OUTPUT DISABLE

With OE at a logic-HIGH level (VIH), the device out-

puts are disabled. Output pins (I/O0 - I/O15) are placed

in a HIGH impedance state.

STANDBY

CE at a logic HIGH level (VIH) places the device in

standby mode which substantially reduces device

power consumption. I/O0 - I/O15 outputs are placed in

a HIGH-impedance state independent of OE. If dese-

lected during block erase or word write, the device con-

tinues functioning, and consuming active power until

the operation completes.

DEEP POWER-DOWN

RP at VIL initiates the deep power down mode.

In read modes, RP-LOW deselects the memory,

places output drivers in a HIGH-impedance state and

turns off all internal circuits. RP must be held LOW for

a minimum of 100 ns. Time tPHQV is required after

return from power-down until initial memory access

outputs are valid. After this wake-up interval, normal

operation is restored. The CUI is reset to read array

mode and status register is set to 80H.

During block erase or word write modes, RP-LOW

will abort the operation. Memory contents being altered

are no longer valid; the data may be partially erased or

written. Time tPHWL is required after RP goes to logic

HIGH (VIH) before another command can be written.

As with any automated device, it is important to

assert RP during system reset. When the system

comes out of reset, it expects to read from flash mem-

ory. Automated flash memories provide status informa-

tion when accessed during block erase or word write

modes. If a CPU reset occurs with no flash memory

reset, proper CPU initialization may not occur because

the flash memory may be providing status information

instead of array data. SHARP’s flash memories allow

proper CPU initialization following a system reset

through the use of RP input. In this application, RP is

controlled by the same RESET signal that resets the

system CPU.

READ IDENTIFIER CODES OPERATION

The read identifier codes operation outputs the manu-

facturer code and device codes, the system CPU can

automatically match the device with its proper algorithms.

7FFFF

RESERVED FOR

FUTURE IMPLEMENTATION

00001

00000

DEVICE CODE

MANUFACTURER CODE

1338A-5

Figure 5. Device Identifier Code Memory Map

WRITE

Writing commands to the CUI enable reading of

device data and identifier codes. They also control

inspection and clearing of the status register.

When VCC = VCC1 and VPP = VPPH, the CUI addi-

tionally controls block erasure and word write. The

Block Erase command requires appropriate command

data and an address within the block to be erased. The

Word Write command requires the command and

address of the location to be written.

The CUI does not occupy an addressable memory

location. It is written when WE and CE are active. The

address and data needed to execute a command are

latched on the rising edge of WE or CE (whichever

goes HIGH first). Standard microprocessor write tim-

ings are used. Figure 13 and 14 illustrate WE and CE

controlled write operations.

10

Data Sheet

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