MK1714-02R Просмотр технического описания (PDF) - Integrated Circuit Systems
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MK1714-02R Datasheet PDF : 5 Pages
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MK1714-02
Spread Spectrum Multiplier Clock
Electrical Specifications
Parameter
Conditions
ABSOLUTE MAXIMUM RATINGS (note 1)
Minimum Typical Maximum Units
Supply voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5 V
Ambient Operating Temperature
0
70
°C
MK1714-02RI only
-40
85
°C
Soldering Temperature
Max of 10 seconds
260
°C
Storage temperature
-65
DC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)
150
°C
Operating Voltage, VDD
3.0
5.5
V
Input High Voltage, VIH, X1/ICLK only
Clock input
VDD/2 + 1 VDD/2
V
Input Low Voltage, VIL, X1/ICLK only
Clock input
VDD/2 VDD/2 - 1 V
Input High Voltage, VIH
Select inputs, OE, PD
2
V
Input Low Voltage, VIL
Select inputs, OE, PD
0.8
V
Output High Voltage, VOH
VDD=3.3V, IOH=-8mA 2.4
V
Output Low Voltage, VOL
VDD=3.3V, IOL=8mA
0.4
V
Output High Voltage, VOH, VDD = 3.3 or 5V IOH=-8mA
VDD-0.4
V
Operating Supply Current, IDD, at 5V
No Load, note 2
40
mA
Operating Supply Current, IDD, at 3.3V
No Load, note 2
26
mA
Short Circuit Current, VDD = 3.3
Each output
±50
mA
Input Capacitance
Except X1, X2
7
pF
Internal Pull-up or Pull-down Resistor
Except X1
500
kΩ
AC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)
Input Crystal Frequency
10
25
MHz
Input Clock Frequency
See page 3
10
150
MHz
Output Clock Rise Time
0.8 to 2.0V, no load
1.5
ns
Output Clock Fall Time
2.0 to 0.8V, no load
1.5
ns
Output Clock Duty Cycle
At VDD/2
40
50
60
%
One Sigma Jitter, CLK
40
ps
Absolute Jitter, CLK
±160
ps
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. Multiplier of x1, all clocks at highest frequencies.
External Components
The MK1714 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01µF should be connected between VDD and GND (on pins 4 and 7), as close to the chip
as possible. A series termination resistor of 33 Ω may be used for each clock output. The crystal must be
connected as close to the chip as possible. The crystal should be a fundamental mode and parallel resonant.
If accurate tuning is required, crystal capacitors should be connected from pins X1 to ground and X2 to
ground. The value of these capacitors is given by the following equation, where CL is the crystal load
capacitance: Crystal caps (pF) = (CL-6) x 2. So for a crystal with 20pF load capacitance, two 28 pF caps
should be used. If a clock input is used, drive it into X1 and leave X2 unconnected.
MDS 1714-02 C
4
Revision 120400
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
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