VSC9111 Просмотр технического описания (PDF) - Vitesse Semiconductor
Номер в каталоге
Компоненты Описание
производитель
VSC9111 Datasheet PDF : 14 Pages
| |||
Target Specification
VSC9111
VITESSE
SEMICONDUCTOR CORPORATION
SONET/SDH 2.5Gb/s
Transport Terminating Transceiver
Pin
RTOHVALID
RTOHFP
RTOH[3..0]
TSPCLK_1
TSPFP_1
TSPREN_1
TSPDAT_1
TSPCLK_2
Name
I/O
Receive Transport
Overhead Valid
O
Receive Transport
Overhead Frame Pulse
O
Receive Transport
Overhead Data
O
Transmit Special
Purpose Clock 1
O
Transmit Special
Purpose Frame Pulse O
1
Transmit Special
Purpose Read Enable O
1
Transmit Special
Purpose Data 1
I
Transmit Special
Purpose Clock 2
O
Freq
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Description
Valid qualifier for the receive transport overhead port.
RTOHVALID is asserted (programmable level) when there is
valid data on RTOH[3..0]. RTOHVALID changes on the
falling edge of RTOHCLK.
Frame reference for the receive transport overhead port.
RTOHFP is a one clock cycle wide pulse coincident with the
first bit(s) of the first A1 being output on RTOH[3..0].
RTOHFP changes on the falling edge of RTOHCLK.
Data output for the receive transport overhead (section and
line) bytes extracted from the incoming STS-48 signal.
RTOH[3..0] changes on the falling edge of RTOHCLK.
Mode 1: RTOH[3] carries the transport overhead from STS-
12 #1 (first interleaved STS-12), RTOH[2] carries the
transport overhead from STS-12 #2, etc.
Mode 2: RTOH[3..0] carries the entire transport overhead in
the order the overhead bytes are received. The most
significant nibble (first received) is output first. RTOH[3] is
the most significant bit.
Clock reference for the transmit special purpose serial input
port 1. The clock is a 2.16MHz, 50% duty-cycle signal
(optionally gapped to match the bandwidth of TSPDAT_1).
Frame reference for the special purpose serial output port
TSPDAT_1.
Mode 1 (TSPCLK_1 continuous): The frame pulse is a one
clock cycle wide pulse indicating the start of a new data
stream on TSPDAT_1. When TSPFP_1 is asserted, the first
bit of TSPDAT_1 is sampled on the second rising edge
thereafter. TSPFP_1 changes on the falling edge of
TSPCLK_1.
Mode 2 (TSPCLK_1 gapped): The frame pulse is a one clock
cycle wide pulse (variable width due to the gapped clock)
indicating the start of a new data stream on TSPDAT_1.
When TSPFP_1 is asserted, the first bit of TSPDAT_1 is
sampled on the second rising edge thereafter. TSPFP_1
changes on the falling edge of TSPCLK_1.
Read enable signal for the TSPDAT_1 data stream. The
response latency from TSPREN_1 is asserted until
TSPDAT_1 is sampled is programmable. TSPREN_1 changes
on the falling edge of TSPCLK_1.
Serial data input for transmit special purpose port 1.
TSPDAT_1 is sampled on the rising edge of TSPCLK_1.
Clock reference for the transmit special purpose serial input
port 2. The clock is a 2.16MHz, 50% duty-cycle signal
(optionally gapped to match the bandwidth of TSPDAT_2).
G52199-0, Rev. 1.2
3/8/99
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 9
Share Link: 