TDAT021G2 Просмотр технического описания (PDF) - Agere -> LSI Corporation

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TDAT021G2

SONET/SDH 155/622/2488 Mbits/s Data Interfaces

Agere -> LSI Corporation 

Advisory

May 2001

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Microprocessor Interface (MPU)

MPU1. Interface to Motorola* MC68360 Processor Is Not Glueless

The interface between the Motorola MC68360 processor and TDAT042G5 requires intervening logic because of

the following incompatibilities in the specifications of these two devices. For a 33 MHz microprocessor clock rate,

the Motorola MC68360 series processors can be interfaced to TDAT042G5 without intervening glue logic, if used

without DT and if programmed for six wait-states. If a user wishes not to use the wait-states, then the chip select

applied to TDAT042G5 must be held low until the address changes. Details are given below.

Chip Select Timing

The TDAT042G5 CS input signal requirements are not compatible with the Motorola MC68360 series processor

CSx output signals. TDAT042G5 timing does not allow simultaneous deassertion of CS and ADS signals. Chip

select applied to TDAT042G5 must be held low for at least 5 ns after the MC68360 deasserts ADS.

Workaround: Use external glue logic to decode the address to generate CS, or provide microprocessor interface

signals meeting the requirements of TDAT042G5.

DT Timing

If the Motorola MC68360 processor CSx signal is used to drive the TDAT042G5 CS, then TDAT042G5 DT output

does not satisfy the MC68360 processor DSACK timing requirement. DT is not pulled to 1 before it is placed in a

high-impedance state. This causes the next MPU cycle to be terminated early.

Workaround: Place a 1 kΩ resistor from DT to VDDD.

Corrective Action

Corrective action for MPU1 has not been determined.

MPU2. Synchronous Microprocessor Interface Mode Is Nonfunctional

The synchronous microprocessor interface mode, MPMODE = 1 (pin D8), functions as described in the advance

data sheet, but causes data errors. Placing TDAT042G5 in the synchronous mode and placing a clock on MPCLK

(pin C8) will cause the data passing through the device to be corrupted. Data errors are generated at a rate of 1%

or less of corrupted packets.

Workaround

Use the TDAT042G5 in the asynchronous microprocessor mode, MPMODE = 0, with no clock applied to MPCLK.

Corrective Action

This condition will be resolved in version 1A of the device.

* Motorola is a registered trademark of Motorola, Inc.

Agere Systems Inc.

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