MG73PB08 Просмотр технического описания (PDF) - Oki Electric Industry

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MG73PB08

0.25µm Sea of Gates and Customer Structured Arrays

Oki Electric Industry 

––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– s MG113P/114P/115P/73P/74P/75P s

Figure 8 shows an array base after placement of the optimized memory macrocells.

High-density RAM

Mega macrocells

Figure 8. Optimized Memory Macrocell Floor Plan

3. Place and route logic into the array transistors.

- Oki Design Center engineers use layout software and customer performance specifications

to connect the random logic and optimized memory macrocells.

Figure 9 marks the area in which placement and routing is performed with cross hatching.

Figure 9. Random Logic Place and Route

Oki Semiconductor

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