MG74PB08 Просмотр технического описания (PDF) - Oki Electric Industry

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MG74PB08

0.25µm Sea of Gates and Customer Structured Arrays

Oki Electric Industry 

––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– s MG113P/114P/115P/73P/74P/75P s

DC Characteristics (VDD Core = 2.25 to 2.75 V, VDD I/O = 2.25 to 2.75 V, VSS = 0 V, Tj = -40° to +125°C)

Parameter

Symbol

Conditions

Rated Value

Min.

Typ. [1]

Max.

Unit

High-level input voltage

VIH

Low-level input voltage

VIL

TTL- level Schmitt

Vt+

Trigger input buffer

Threshold voltage

Vt-

∆Vt

High-level output voltage (Output buffer)

VOH

Low-level output voltage (Output buffer)

VOL

High-level input current (Input buffer)

IIH

Low-level input current (Normal input buffer)

IIL

3-state output leakage current

IOZH

(Normal input buffer)

IOZL

Stand-by current [2]

IDDQ

TTL input (normal), VDD=VDD I/O

1.7

TTL input (normal)

-0.3

-

VDD + 0.3

-

0.7

TTL input (normal)

-

-

1.7

0.6

-

-

Vt+ - Vt-

-

0.4

-

V

IOH = -100 µA, VDD=VDD I/O

VDD - 0.2

-

-

IOH = -0.5, -1, -2, -3, -4, -6, -12 mA 1.95

-

-

IOL = 100 µA

-

-

0.2

IOL = -0.5, 1, 2, 3, 4, 6, 12 mA

-

-

0.45

VIH = VDD

VIL = VSS

-50

-

50

µA

-50

-

50

VIL = VSS (3-kΩ pull-up)

-

-0.8

-

mA

VOH = VDD

VOL = VSS

-50

-

50

µA

-50

-

50

VOL = VSS (3-kΩ pull-up)

-

-0.8

-

mA

Output open, VIH = VDD, VIL = VSS

Design Dependent

µA

1. Typical condition is VDD I/O = 2.5 V, VDD Core = 2.5 V, and Tj = 25°C for a typical process.

2. RAM/ROM should be in powerdown mode.

Oki Semiconductor

9

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