MT9080AP Просмотр технического описания (PDF) - Mitel Networks
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MT9080AP Datasheet PDF : 24 Pages
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MT9080 CMOS
CK
16
D0-D15
FP
16
D0o-D15o
A0-A15
CS
DS
R/W
DTA
CD
ME
ODE
MODE
ZY X
0/1 1 0
Fig. 7 - Connect Memory Modes Pinout
Data is clocked out on D0o-D15o from memory
locations addressed sequentially by the internal
counter. This counter is incremented every second
clock period and is reset with FP. The frequency of
the clock signal used should be twice the data rate.
A timing diagram showing the relationship between
the data output and the clock signal is presented in
Fig. 8. With a clock rate of 16.384 MHz, the
maximum number of addresses that can be
generated in an 8 kHz frame period is 1024.
FP
CK
Data
1023
0
Out
Connect Memory Mode-2
Connect Memory Mode-2 is designed specifically for
2048 channel switching applications. Data is clocked
out on D0o-D15o with every rising clock edge from
memory locations addressed sequentially by the
internal counter (see Figure 9). This counter is
incremented with each clock period and is reset with
FP or when a count of 2047 is reached.
FP
CK
DATA
OUTPUT
2047
0
AAAAAAAAAAAAA
1
2
Fig. 9 - Connect Memory Mode-2 Functional
Timing
The clock frequency should be 16.384 MHz for a
connection memory designed to support a 2048
channel switch.
Microprocessor access is similar to Connect Memory
Mode-1.
Counter Mode
This mode is designed for 2048 channel switching
applications. In the counter mode all read and write
addresses are generated sequentially by the internal
11 bit counter. The 11 bit counter is incremented
with each clock pulse. It will wrap around when it
reaches a count of binary 2047 or when it is reset by
FP. The active input/output pins in this mode are
illustrated in Fig. 10.
Fig. 8 - Connect Memory Mode-1 Functional
Timing
Microprocessor access timing is shown in Figures 28
and 29. During a microprocessor read cycle, DS low
indicates to the SMX that the processor is ready to
receive data. The SMX responds by pulling DTA low
when there is valid data present on the bus. The
processor latches the data in and sets DS high. The
SMX completes the bus cycle by disabling the DTA.
DS should be kept low until after DTA is issued by
the SMX. CS, R/W and the address lines should
also be asserted for the duration of the access. A
MPU write cycle is similar to the read cycle. Data will
be latched into the device approximately three clock
(CK) cycles after DS goes low. When the device
has latched the data in, it will pull DTA low. DS can
subsequently be set high.
CK
FP
D0i-D15i
16
D0o-D15o
16
CS
ODE
DTA
CD R/W ME X Y Z
10 0
All other inputs should
be tied Low
Fig. 10 - Counter Mode Pinout
2-108
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