DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

MT9080AP Просмотр технического описания (PDF) - Mitel Networks

Номер в каталоге
Компоненты Описание
производитель
MT9080AP
Mitel
Mitel Networks Mitel
MT9080AP Datasheet PDF : 24 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
CMOS MT9080
memory. The delay through the matrix can be
optimized for specific applications by selectively
enabling one of the two modes. Data Memory-1
(DM-1) is designed for voice switching applications
where it is generally desirable to minimize delay
through the switch. As mentioned earlier in the
DM-1 description, the delay through the switch
depends upon the difference between the input
channel timeslot and the output channel timeslot.
Consecutive output channels switched from
non-contiguous input channels will not always
originate from the same input frame. For example, if
channels 3, 6 and 8 are to be switched to channels
5, 6 and 7; output channel 5 will contain data input in
the current frame, while channels 6 and 7 will contain
data clocked in one frame earlier. Data Memory-2
(DM-2) is designed for data switching applications
where concatenation of a number of channels is
often necessary. Data clocked out of the device will
originate from the previous frame, regardless of the
input/output time difference. There is one exception,
when channel 1023 is switched to channel 0, the
contents of Channel 0 will not originate from the
previous frame but rather from the frame before it.
The capability to selectively change between DM-1
and DM-2 allows a single switch to handle both voice
and data effectively.
External bus drivers can be controlled with D13 of
the Connection Memory data bus. This bit will be
output along with the remaining bits one channel
Parallel Input Data
16
FP#1
Timing
CK
Generator
FP#2
D0i-D15i
FP
CK
A0-A9
SMX #1
DM-1/2
DATA
MEMORY
ODE ME
D0o-D15o
Parallel Output Data
16
A10-A15
+5
R/W
CS
DS
MODE
ZYX
10
D0o-D9o D10o D11o D12o D13o
External
Tristate
Control
CK
FP
CD
D0-D15
SMX #2
CM-1
CONNECTION
MEMORY
R/W DTA DS
X
MODE Y
Z
A11-A15
A10
CS
A0-A9
D0-D15
IRQ
R/W HALT DS
16-BIT MPU
0
1
0
+5
Address
Decode
Note: All other inputs not shown in this diagram should be connected to GND.
Figure 15 - 1024 Channel Switch Matrix
2-111

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]