CY7C9335 Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C9335 Datasheet PDF : 8 Pages
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CY7C9335
Electrical Characteristics Over the Operating Range
Parameter
Description
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Load Current
IOZ
Output Leakage Current
IOS
Output Short Circuit Current[3, 4]
Test Conditions
IOH = −3.2 mA, VCC = Min.
IOL = 16.0 mA, VCC = Min
Note 2
Note 2
GND ≤ VI ≤ VCC
GND ≤ VO ≤ VCC, Output Disabled
VCC = Max., VOUT = 0.5V
Min.
2.4
2.0
−0.5
−10
−50
−30
Max.
Unit
V
0.5
V
7.0
V
0.8
V
+10
µA
+50
µA
−160
mA
Capacitance[4]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
f = 1 MHz, VCC = 5.0V
Max.
Unit
10
pF
12
pF
AC Test Loads and Waveforms
TTL OUTPUTS
5V
OUTPUT
35 pF
INCLUDING
JIG AND
SCOPE
238Ω
(a)
238Ω
5V
3.0V
OUTPUT
170Ω
5 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
OUTPUT
170 GND
< 2 ns
(b)
THÉVENIN
99 Ω
EQUIVALENT
2.08V
ALL INPUT PULSES
90%
10%
90%
10%
< 2 ns
7C9335–9
Switching Characteristics Over the Operating Range[5]
CY7C9335-27 CY7C9335-40
Parameter
Description
Min. Max. Min. Max. Unit
tPD
Input to Output (DVB_EN to RF only)
20
15
ns
tSD
Input Data Set-Up Time to CKR
10
8
ns
tHD
Input Data Hold Time to CKR
0
0
ns
tCPRH
CKR Pulse Width HIGH
6.5
6.5
ns
tCPRL
tCKR
CKR Pulse Width LOW
Read Clock Cycle[6]
6.5
6.5
ns
30 62.5 25 62.5
ns
tA
Output Access Time from CKR
10
8
ns
tH
Output Hold Time from CKR
4
3
ns
tEA
Input to Output Enable
tER
Input to Output Disable [7]
24
20
ns
24
20
ns
Notes:
1. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. These are absolute values with respect to device ground. All overshoots with respect to system or tester noise are included.
3. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test
problems caused by tester ground degradation.
4. Tested initially and after any design or process changes that may effect these parameters.
5. All AC parameters are with all outputs switching.
6. The clock period may be extended by up to 90% for a single clock cycle when framing occurs in DVB-ASI mode.
7. Test load (b) used for this parameter. Test load (a) used for all other AC parameters.
Document #: 38-02011 Rev. *A
Page 5 of 8
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