Z80195 Просмотр технического описания (PDF) - Zilog

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производитель

Z80195

SMART PERIPHERAL CONTROLLERS

Zilog 

Zilog

T1

0

Address

/IROQ

/RD

/WR

PRELIMINARY

Z80185/Z80195

SMART PERIPHERAL CONTROLLERS

I/O Read Cycle

T2

TW

T3

I/O Write Cycle

T1

T2

TW

T3

28

29

28

29

9

13

22

25

Figure 6. CPU Timing

CPU or DMA Read/Write Cycle

T1

T2

Tw

T3

Ø

TOUT//DREQ

(At level

sense)

TOUT//DREQ

(At edge

sence)

ST

45

45

45 [2]

46 [1]

[3]

17

DMA Control Signals

[1] tDRQS and tDRQH are specified for the rising edge of clock followed by T3.

[2] tDRQS and tDRQH are specified for the rising edge of clock.

[3] DMA cycle starts.

[4] CPU cycle starts.

Figure 7. DMA Control Signals

T1

18

[4]

8

DS971850301

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